mirror of
https://github.com/RIOT-OS/RIOT.git
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05f114d0af
- most were trivial
- missing group close or open
- extra space
- no doxygen comment
- name commad might open an implicit group
this hould also be implicit cosed but does not happen somtimes
- crazy: internal declared groups have to be closed internal
252 lines
15 KiB
C
252 lines
15 KiB
C
/*
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* Copyright (C) 2019 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup drivers_stmpe811
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*
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* @{
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* @file
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* @brief Constants for STMPE811
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef STMPE811_CONSTANTS_H
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#define STMPE811_CONSTANTS_H
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#include "stmpe811.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define STMPE811_I2C_ADDR_DEFAULT (0x41) /**< Default I2C address */
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#define STMPE811_CHIP_ID_VALUE (0x0811) /**< Chip ID */
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/**
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* @name Registers
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* @{
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*/
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#define STMPE811_CHIP_ID (0x00) /**< STMPE811 Device identification */
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#define STMPE811_ID_VER (0x02) /**< STMPE811 Revision number */
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#define STMPE811_SYS_CTRL1 (0x03) /**< Reset control */
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#define STMPE811_SYS_CTRL2 (0x04) /**< Clock control */
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#define STMPE811_SPI_CFG (0x08) /**< SPI interface configuration */
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#define STMPE811_INT_CTRL (0x09) /**< Interrupt control register */
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#define STMPE811_INT_EN (0x0A) /**< Interrupt enable register */
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#define STMPE811_INT_STA (0x0B) /**< Interrupt status register */
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#define STMPE811_GPIO_EN (0x0C) /**< GPIO interrupt enable register */
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#define STMPE811_GPIO_INT_STA (0x0D) /**< GPIO interrupt status register */
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#define STMPE811_ADC_INT_EN (0x0E) /**< ADC interrupt enable register */
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#define STMPE811_ADC_INT_STA (0x0F) /**< ADC interface status register */
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#define STMPE811_GPIO_SET_PIN (0x10) /**< GPIO set pin register */
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#define STMPE811_GPIO_CLR_PIN (0x11) /**< GPIO clear pin register */
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#define STMPE811_MP_STA (0x12) /**< GPIO monitor pin state register */
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#define STMPE811_GPIO_DIR (0x13) /**< GPIO direction register */
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#define STMPE811_GPIO_ED (0x14) /**< GPIO edge detect register */
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#define STMPE811_GPIO_RE (0x15) /**< GPIO rising edge register */
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#define STMPE811_GPIO_FE (0x16) /**< GPIO falling edge register */
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#define STMPE811_GPIO_ALT_FUNCTION (0x17) /**< Alternate function register */
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#define STMPE811_ADC_CTRL1 (0x20) /**< ADC control */
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#define STMPE811_ADC_CTRL2 (0x21) /**< ADC control */
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#define STMPE811_ADC_CAPT (0x22) /**< To initiate ADC data acquisition */
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#define STMPE811_ADC_DATA_CHO (0x30) /**< ADC channel 0 */
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#define STMPE811_ADC_DATA_CH1 (0x32) /**< ADC channel 1 */
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#define STMPE811_ADC_DATA_CH2 (0x34) /**< ADC channel 2 */
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#define STMPE811_ADC_DATA_CH3 (0x36) /**< ADC channel 3 */
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#define STMPE811_ADC_DATA_CH4 (0x38) /**< ADC channel 4 */
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#define STMPE811_ADC_DATA_CH5 (0x3A) /**< ADC channel 5 */
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#define STMPE811_ADC_DATA_CH6 (0x3C) /**< ADC channel 6 */
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#define STMPE811_ADC_DATA_CH7 (0x3E) /**< ADC channel 7 */
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#define STMPE811_TSC_CTRL (0x40) /**< 4-wire tsc setup */
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#define STMPE811_TSC_CFG (0x41) /**< Tsc configuration */
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#define STMPE811_WDW_TR_X (0x42) /**< Window setup for top right X */
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#define STMPE811_WDW_TR_Y (0x44) /**< Window setup for top right Y */
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#define STMPE811_WDW_BL_X (0x46) /**< Window setup for bottom left X */
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#define STMPE811_WDW_BL_Y (0x48) /**< Window setup for bottom left Y */
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#define STMPE811_FIFO_TH (0x4A) /**< FIFO level to generate interrupt */
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#define STMPE811_FIFO_CTRL_STA (0x4B) /**< Current status of FIFO */
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#define STMPE811_FIFO_SIZE (0x4C) /**< Current filled level of FIFO */
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#define STMPE811_TSC_DATA_X (0x4D) /**< Data port for tsc data access */
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#define STMPE811_TSC_DATA_Y (0x4F) /**< Data port for tsc data access */
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#define STMPE811_TSC_DATA_Z (0x51) /**< Data port for tsc data access */
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#define STMPE811_TSC_DATA_XYZ (0x52) /**< Data port for tsc data access */
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#define STMPE811_TSC_DATA_INC (0x57) /**< Data port for tsc auto-increment data access */
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#define STMPE811_TSC_DATA_NON_INC (0xD7) /**< Data port for tsc non auto-increment data access */
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#define STMPE811_TSC_FRACTION_Z (0x56) /**< Touchscreen controller FRACTION_Z */
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#define STMPE811_TSC_DATA (0x57) /**< Data port for tsc data access */
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#define STMPE811_TSC_I_DRIVE (0x58) /**< Touchscreen controller drivel */
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#define STMPE811_TSC_SHIELD (0x59) /**< Touchscreen controller shield */
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#define STMPE811_TEMP_CTRL (0x60) /**< Temperature sensor setup */
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#define STMPE811_TEMP_DATA (0x61) /**< Temperature data access port */
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#define STMPE811_TEMP_TH (0x62) /**< Threshold for temp controlled int */
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/** @} */
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/**
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* @name SYS_CTRL1 register bitfields
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* @{
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*/
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#define STMPE811_SYS_CTRL1_HIBERNATE (1 << 0) /**< Hibernate the device*/
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#define STMPE811_SYS_CTRL1_SOFT_RESET (1 << 1) /**< Trigger software reset */
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/** @} */
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/**
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* @name SYS_CTRL2 register bitfields
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* @{
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*/
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#define STMPE811_SYS_CTRL2_ADC_OFF (1 << 0) /**< Disable ADC */
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#define STMPE811_SYS_CTRL2_TSC_OFF (1 << 1) /**< Disable Touchscreen*/
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#define STMPE811_SYS_CTRL2_GPIO_OFF (1 << 2) /**< Disable GPIO */
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#define STMPE811_SYS_CTRL2_TS_OFF (1 << 3) /**< Disable Temperature sensor */
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/** @} */
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/**
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* @name SPI_CFG register bitfields
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* @{
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*/
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#define STMPE811_SPI_CFG_SPI_CLK_MOD0 (1 << 0) /**< SCAD/A0 pin during power-up reset */
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#define STMPE811_SPI_CFG_SPI_CLK_MOD1 (1 << 1) /**< SCAD/A0 pin during power-up reset */
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#define STMPE811_SPI_CFG_AUTO_INCR (1 << 2) /**< SPI transactions internal autoincrement */
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/** @} */
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/**
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* @name INT_CTRL register bitfields
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* @{
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*/
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#define STMPE811_INT_CTRL_INT_POLARITY (1 << 2) /**< Configure interrupt polarity (falling or raising) */
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#define STMPE811_INT_CTRL_INT_TYPE (1 << 1) /**< Configure interrupt type (edge or level) */
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#define STMPE811_INT_CTRL_GLOBAL_INT (1 << 0) /**< Enable global interrupt */
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/** @} */
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/**
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* @name INT_EN register bitfields
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* @{
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*/
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#define STMPE811_INT_EN_TOUCH_DET (1 << 0) /**< Enable touch detection interrupt */
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#define STMPE811_INT_EN_FIFO_TH (1 << 1) /**< Enable FIFO threshold interrupt */
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#define STMPE811_INT_EN_FIFO_OFLOW (1 << 2) /**< Enable FIFO overflow interrupt */
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#define STMPE811_INT_EN_FIFO_FULL (1 << 3) /**< Enable FIFO full interrupt */
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#define STMPE811_INT_EN_FIFO_EMPTY (1 << 4) /**< Enable FIFO empty interrupt */
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#define STMPE811_INT_EN_TEMP_SENS (1 << 5) /**< Enable temperature sensor interrupt */
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#define STMPE811_INT_EN_ADC (1 << 6) /**< Enable ADC interrupt */
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#define STMPE811_INT_EN_GPIO (1 << 7) /**< Enable GPIO interrupt */
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/** @} */
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/**
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* @name ADC_CTRL1 register bitfields
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* @{
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*/
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#define STMPE811_ADC_CTRL1_SAMPLE_TIME_POS (4) /**< Sample time bits shift position */
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#define STMPE811_ADC_CTRL1_SAMPLE_TIME_36 (0b000) /**< Conversion time: 36 cycles */
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#define STMPE811_ADC_CTRL1_SAMPLE_TIME_44 (0b001) /**< Conversion time: 44 cycles */
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#define STMPE811_ADC_CTRL1_SAMPLE_TIME_56 (0b010) /**< Conversion time: 56 cycles */
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#define STMPE811_ADC_CTRL1_SAMPLE_TIME_64 (0b011) /**< Conversion time: 64 cycles */
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#define STMPE811_ADC_CTRL1_SAMPLE_TIME_80 (0b100) /**< Conversion time: 80 cycles */
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#define STMPE811_ADC_CTRL1_SAMPLE_TIME_96 (0b101) /**< Conversion time: 96 cycles */
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#define STMPE811_ADC_CTRL1_SAMPLE_TIME_124 (0b110) /**< Conversion time: 124 cycles */
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#define STMPE811_ADC_CTRL1_MOD_12B (1 << 3) /**< Enable 12 bit ADC (10bit if 0) */
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/** @} */
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/**
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* @name ADC_CTRL2 register bitfields
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* @{
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*/
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#define STMPE811_ADC_CTRL2_FREQ_1_625MHZ (0b00) /**< ADC clock frequency 1.625MHz */
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#define STMPE811_ADC_CTRL2_FREQ_3_25MHZ (0b01) /**< ADC clock frequency 3.25MHz */
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#define STMPE811_ADC_CTRL2_FREQ_6_5MHZ (0b10) /**< ADC clock frequency 6.5MHz */
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#define STMPE811_ADC_CTRL2_FREQ_6_5_2MHZ (0b11) /**< ADC clock frequency 6.5MHz */
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/** @} */
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/**
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* @name TSC_CTRL register bitfields
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* @{
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*/
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#define STMPE811_TSC_CTRL_EN (1 << 0) /**< Enable touchscreen */
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#define STMPE811_TSC_CTRL_OPMOD_POS (1) /**< Operating mode bit shift position */
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#define STMPE811_TSC_CTRL_OPMOD_XYZ (0b000) /**< X,Y,Z acquisition */
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#define STMPE811_TSC_CTRL_OPMOD_XY_ONLY (0b001) /**< X,Y only acquisition */
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#define STMPE811_TSC_CTRL_OPMOD_X_ONLY (0b010) /**< X only acquisition */
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#define STMPE811_TSC_CTRL_OPMOD_Y_ONLY (0b011) /**< Y only acquisition */
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#define STMPE811_TSC_CTRL_OPMOD_Z_ONLY (0b100) /**< Z only acquisition */
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#define STMPE811_TSC_CTRL_TRACK_POS (4) /**< Movement tracking index bit shift position */
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#define STMPE811_TSC_CTRL_TRACK_NO (0b000) /**< No window tracking */
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#define STMPE811_TSC_CTRL_TRACK_4 (0b001) /**< Tracking index 4 */
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#define STMPE811_TSC_CTRL_TRACK_8 (0b010) /**< Tracking index 8 */
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#define STMPE811_TSC_CTRL_TRACK_16 (0b011) /**< Tracking index 16 */
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#define STMPE811_TSC_CTRL_TRACK_32 (0b100) /**< Tracking index 32 */
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#define STMPE811_TSC_CTRL_TRACK_64 (0b101) /**< Tracking index 64 */
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#define STMPE811_TSC_CTRL_TRACK_92 (0b110) /**< Tracking index 92 */
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#define STMPE811_TSC_CTRL_TRACK_127 (0b111) /**< Tracking index 127 */
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#define STMPE811_TSC_CTRL_STA (1 << 7) /**< Touchscreen status (1: touch detected, 0: no touch detected), read-only */
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/** @} */
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/**
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* @name TSC_CFG register bitfields
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* @{
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*/
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#define STMPE811_TSC_CFG_AVE_CTRL_POS (6) /**< Average control bit shift position */
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#define STMPE811_TSC_CFG_AVE_CTRL_1 (0b00) /**< Average control, 1 sample */
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#define STMPE811_TSC_CFG_AVE_CTRL_2 (0b01) /**< Average control, 2 sample */
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#define STMPE811_TSC_CFG_AVE_CTRL_4 (0b10) /**< Average control, 4 sample */
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#define STMPE811_TSC_CFG_AVE_CTRL_8 (0b11) /**< Average control, 8 sample */
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#define STMPE811_TSC_CFG_TOUCH_DET_DELAY_POS (3) /**< Touch detection delay bit shift position */
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#define STMPE811_TSC_CFG_TOUCH_DET_DELAY_10US (0b000) /**< Touch detection 10us delay */
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#define STMPE811_TSC_CFG_TOUCH_DET_DELAY_50US (0b001) /**< Touch detection 50us delay */
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#define STMPE811_TSC_CFG_TOUCH_DET_DELAY_100US (0b010) /**< Touch detection 100us delay */
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#define STMPE811_TSC_CFG_TOUCH_DET_DELAY_500US (0b011) /**< Touch detection 500us delay */
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#define STMPE811_TSC_CFG_TOUCH_DET_DELAY_1MS (0b100) /**< Touch detection 1ms delay */
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#define STMPE811_TSC_CFG_TOUCH_DET_DELAY_5MS (0b101) /**< Touch detection 5ms delay */
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#define STMPE811_TSC_CFG_TOUCH_DET_DELAY_10MS (0b110) /**< Touch detection 10ms delay */
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#define STMPE811_TSC_CFG_TOUCH_DET_DELAY_50MS (0b111) /**< Touch detection 50ms delay */
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#define STMPE811_TSC_CFG_SETTLING_10US (0b000) /**< Settling time 10us */
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#define STMPE811_TSC_CFG_SETTLING_100US (0b001) /**< Settling time 100us */
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#define STMPE811_TSC_CFG_SETTLING_500US (0b010) /**< Settling time 500us */
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#define STMPE811_TSC_CFG_SETTLING_1MS (0b011) /**< Settling time 1ms */
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#define STMPE811_TSC_CFG_SETTLING_5MS (0b100) /**< Settling time 5ms */
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#define STMPE811_TSC_CFG_SETTLING_10MS (0b101) /**< Settling time 10ms */
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#define STMPE811_TSC_CFG_SETTLING_50MS (0b110) /**< Settling time 50ms */
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#define STMPE811_TSC_CFG_SETTLING_100MS (0b111) /**< Settling time 100ms */
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/** @} */
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/**
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* @name FIFO_CTRL_STA register bitfields
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* @{
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*/
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#define STMPE811_FIFO_CTRL_STA_RESET (1 << 0) /**< Reset FIFO */
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/** @} */
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/**
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* @name TSC_FRACTION_Z register bitfields
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* @{
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*/
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#define STMPE811_TSC_FRACTION_Z_0_8 (0b000) /**< Fractional part is 0, whole part is 8 */
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#define STMPE811_TSC_FRACTION_Z_1_7 (0b001) /**< Fractional part is 1, whole part is 7 */
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#define STMPE811_TSC_FRACTION_Z_2_6 (0b010) /**< Fractional part is 2, whole part is 6 */
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#define STMPE811_TSC_FRACTION_Z_3_5 (0b011) /**< Fractional part is 3, whole part is 5 */
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#define STMPE811_TSC_FRACTION_Z_4_4 (0b100) /**< Fractional part is 4, whole part is 4 */
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#define STMPE811_TSC_FRACTION_Z_5_3 (0b101) /**< Fractional part is 5, whole part is 3 */
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#define STMPE811_TSC_FRACTION_Z_6_2 (0b110) /**< Fractional part is 6, whole part is 2 */
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#define STMPE811_TSC_FRACTION_Z_7_1 (0b111) /**< Fractional part is 7, whole part is 1 */
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/** @} */
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/**
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* @name TSC_I_DRIVE register bitfields
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* @{
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*/
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#define STMPE811_TSC_I_DRIVE_50MA (1 << 0) /**< Enable 50mA drive current, 20mA if 0 */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* STMPE811_CONSTANTS_H */
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/** @} */
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