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156 lines
3.2 KiB
C
156 lines
3.2 KiB
C
/*
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* Copyright (C) 2021 Mesotic SAS
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_nrf9160
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* @{
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*
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* @file
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* @brief Shared IRQ handling between SPI and TWI peripherals on the nRF52
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* devices
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*
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* I2C is called TWI (Two Wire Interface) in the datasheets from Nordic
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*
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* @author Dylan Laduranty <dylan.laduranty@mesotic.com>
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*
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* @}
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*/
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#include <assert.h>
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#include "cpu.h"
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#include "mutex.h"
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#include "periph_cpu.h"
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#include "periph_conf.h"
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static spi_twi_irq_cb_t _irq[TWIM_COUNT];
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static void *_irq_arg[TWIM_COUNT];
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static mutex_t _locks[SPIM_COUNT];
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#if TWIM_COUNT != SPIM_COUNT
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#error Possible configuration issue, please update this file
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#endif
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/* I2C and SPI share peripheral addresses */
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static size_t _spi_dev2num(void *dev)
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{
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if (dev == NRF_SPIM0_S) {
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return 0;
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}
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else if (dev == NRF_SPIM1_S) {
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return 1;
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}
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else if (dev == NRF_SPIM2_S) {
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return 2;
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}
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else if (dev == NRF_SPIM3_S) {
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return 3;
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}
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else {
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assert(false);
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return 0;
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}
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}
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static inline size_t _i2c_dev2num(void *dev)
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{
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return _spi_dev2num(dev);
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}
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static const IRQn_Type _isr[] = {
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UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQn,
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UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQn,
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UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQn,
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UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQn
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};
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void spi_twi_irq_register_spi(NRF_SPIM_Type *bus,
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spi_twi_irq_cb_t cb, void *arg)
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{
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size_t num = _spi_dev2num(bus);
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_irq[num] = cb;
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_irq_arg[num] = arg;
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NVIC_EnableIRQ(_isr[num]);
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}
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void spi_twi_irq_register_i2c(NRF_TWIM_Type *bus,
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spi_twi_irq_cb_t cb, void *arg)
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{
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size_t num = _i2c_dev2num(bus);
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_irq[num] = cb;
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_irq_arg[num] = arg;
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NVIC_EnableIRQ(_isr[num]);
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}
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void nrf5x_i2c_acquire(NRF_TWIM_Type *bus,
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spi_twi_irq_cb_t cb, void *arg)
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{
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size_t num = _i2c_dev2num(bus);
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mutex_lock(&_locks[num]);
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_irq[num] = cb;
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_irq_arg[num] = arg;
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}
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void nrf5x_spi_acquire(NRF_SPIM_Type *bus,
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spi_twi_irq_cb_t cb, void *arg)
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{
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size_t num = _spi_dev2num(bus);
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mutex_lock(&_locks[num]);
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_irq[num] = cb;
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_irq_arg[num] = arg;
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}
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void nrf5x_i2c_release(NRF_TWIM_Type *bus)
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{
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size_t num = _i2c_dev2num(bus);
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mutex_unlock(&_locks[num]);
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}
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void nrf5x_spi_release(NRF_SPIM_Type *bus)
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{
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size_t num = _spi_dev2num(bus);
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mutex_unlock(&_locks[num]);
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}
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/* Check if UART driver doesn't already use the same IRQ */
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#ifndef UART_0_ISR
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void isr_uarte0_spim0_spis0_twim0_twis0(void)
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{
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_irq[0](_irq_arg[0]);
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cortexm_isr_end();
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}
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#endif /* ndef UART_0_ISR */
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#ifndef UART_1_ISR
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void isr_uarte1_spim1_spis1_twim1_twis1(void)
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{
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_irq[1](_irq_arg[1]);
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cortexm_isr_end();
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}
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#endif /* ndef UART_1_ISR */
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#ifndef UART_2_ISR
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void isr_uarte2_spim2_spis2_twim2_twis2(void)
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{
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_irq[2](_irq_arg[2]);
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cortexm_isr_end();
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}
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#endif /* ndef UART_2_ISR */
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#ifndef UART_3_ISR
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void isr_uarte3_spim3_spis3_twim3_twis3(void)
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{
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_irq[3](_irq_arg[3]);
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cortexm_isr_end();
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}
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#endif /* ndef UART_3_ISR */
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