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e3d5a70e0c
These are leftovers from before the Cortex-M common ISR vectors were split into vectors_cortexm.c
101 lines
3.3 KiB
C
101 lines
3.3 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_lpc1768
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* @{
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*
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* @file
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* @brief Startup code and interrupt vector definition
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include <stdint.h>
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#include "vectors_cortexm.h"
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/* define a local dummy handler as it needs to be in the same compilation unit
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* as the alias definition */
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void dummy_handler(void) {
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dummy_handler_default();
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}
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/* LPC1768 specific interrupt vector */
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WEAK_DEFAULT void isr_wdt(void);
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WEAK_DEFAULT void isr_timer0(void);
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WEAK_DEFAULT void isr_timer1(void);
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WEAK_DEFAULT void isr_timer2(void);
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WEAK_DEFAULT void isr_timer3(void);
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WEAK_DEFAULT void isr_uart0(void);
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WEAK_DEFAULT void isr_uart1(void);
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WEAK_DEFAULT void isr_uart2(void);
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WEAK_DEFAULT void isr_uart3(void);
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WEAK_DEFAULT void isr_pwm1(void);
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WEAK_DEFAULT void isr_i2c0(void);
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WEAK_DEFAULT void isr_i2c1(void);
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WEAK_DEFAULT void isr_i2c2(void);
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WEAK_DEFAULT void isr_spi(void);
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WEAK_DEFAULT void isr_ssp0(void);
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WEAK_DEFAULT void isr_ssp1(void);
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WEAK_DEFAULT void isr_pll0(void);
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WEAK_DEFAULT void isr_rtc(void);
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WEAK_DEFAULT void isr_eint0(void);
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WEAK_DEFAULT void isr_eint1(void);
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WEAK_DEFAULT void isr_eint2(void);
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WEAK_DEFAULT void isr_eint3(void);
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WEAK_DEFAULT void isr_adc(void);
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WEAK_DEFAULT void isr_bod(void);
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WEAK_DEFAULT void isr_usb(void);
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WEAK_DEFAULT void isr_can(void);
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WEAK_DEFAULT void isr_dma(void);
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WEAK_DEFAULT void isr_i2s(void);
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WEAK_DEFAULT void isr_enet(void);
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WEAK_DEFAULT void isr_rit(void);
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WEAK_DEFAULT void isr_mcpwm(void);
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WEAK_DEFAULT void isr_qei(void);
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WEAK_DEFAULT void isr_pll1(void);
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/* CPU specific interrupt vector table */
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ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
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isr_wdt, /* watchdog timer */
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isr_timer0, /* timer0 */
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isr_timer1, /* timer1 */
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isr_timer2, /* timer2 */
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isr_timer3, /* timer3 */
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isr_uart0, /* uart0 */
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isr_uart1, /* uart1 */
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isr_uart2, /* uart2 */
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isr_uart3, /* uart3 */
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isr_pwm1, /* pwm1 */
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isr_i2c0, /* i2c0 */
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isr_i2c1, /* i2c1 */
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isr_i2c2, /* i2c2 */
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isr_spi, /* spi */
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isr_ssp0, /* ssp0 */
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isr_ssp1, /* ssp1 */
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isr_pll0, /* pll0 (main pll) */
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isr_rtc, /* real time clock */
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isr_eint0, /* external interrupt 0 */
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isr_eint1, /* external interrupt 1 */
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isr_eint2, /* external interrupt 2 */
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isr_eint3, /* external interrupt 3 */
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isr_adc, /* a/d converter */
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isr_bod, /* brown out detect */
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isr_usb, /* usb */
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isr_can, /* can */
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isr_dma, /* gp dma */
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isr_i2s, /* i2s */
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isr_enet, /* ethernet */
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isr_rit, /* repetitive interrupt timer */
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isr_mcpwm, /* motor control pwm */
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isr_qei, /* quadrature encoder interface */
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isr_pll1, /* pll1 (usb pll) */
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};
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