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221 lines
9.7 KiB
C
221 lines
9.7 KiB
C
/******************************************************************************
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* Filename: hw_cpu_rom_table_h
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* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017)
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* Revision: 48345
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_CPU_ROM_TABLE_H__
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#define __HW_CPU_ROM_TABLE_H__
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//*****************************************************************************
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//
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// This section defines the register offsets of
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// CPU_ROM_TABLE component
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//
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//*****************************************************************************
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// System Control Space Component
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#define CPU_ROM_TABLE_O_SCS 0x00000000
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// Data Watchpoint and Trace Component
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#define CPU_ROM_TABLE_O_DWT 0x00000004
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// Flash Patch and Breakpoint Component
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#define CPU_ROM_TABLE_O_FPB 0x00000008
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// Instrumentation Trace Component
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#define CPU_ROM_TABLE_O_ITM 0x0000000C
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// Trace Port Interface Component
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#define CPU_ROM_TABLE_O_TPIU 0x00000010
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// Enhanced Trace Component
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#define CPU_ROM_TABLE_O_ETM 0x00000014
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// End Marker
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#define CPU_ROM_TABLE_O_END 0x00000018
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// System Memory Map Access for DAP
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#define CPU_ROM_TABLE_O_SYSTEM_ACCESS 0x00000FCC
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//*****************************************************************************
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//
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// Register: CPU_ROM_TABLE_O_SCS
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//
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//*****************************************************************************
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// Field: [31:0] SCS
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//
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// Points to the SCS at 0xE000E000.
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// (SCS + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE000E000.
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#define CPU_ROM_TABLE_SCS_SCS_W 32
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#define CPU_ROM_TABLE_SCS_SCS_M 0xFFFFFFFF
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#define CPU_ROM_TABLE_SCS_SCS_S 0
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//*****************************************************************************
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//
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// Register: CPU_ROM_TABLE_O_DWT
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//
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//*****************************************************************************
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// Field: [31:1] DWT
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//
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// Points to the Data Watchpoint and Trace block at 0xE0001000.
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// (2*DWT + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0001000.
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#define CPU_ROM_TABLE_DWT_DWT_W 31
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#define CPU_ROM_TABLE_DWT_DWT_M 0xFFFFFFFE
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#define CPU_ROM_TABLE_DWT_DWT_S 1
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// Field: [0] DWT_PRESENT
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//
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// 0: DWT is not present
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// 1: DWT is present.
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#define CPU_ROM_TABLE_DWT_DWT_PRESENT 0x00000001
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#define CPU_ROM_TABLE_DWT_DWT_PRESENT_BITN 0
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#define CPU_ROM_TABLE_DWT_DWT_PRESENT_M 0x00000001
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#define CPU_ROM_TABLE_DWT_DWT_PRESENT_S 0
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//*****************************************************************************
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//
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// Register: CPU_ROM_TABLE_O_FPB
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//
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//*****************************************************************************
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// Field: [31:1] FPB
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//
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// Points to the Flash Patch and Breakpoint block at 0xE0002000.
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// (2*FPB + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0002000.
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#define CPU_ROM_TABLE_FPB_FPB_W 31
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#define CPU_ROM_TABLE_FPB_FPB_M 0xFFFFFFFE
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#define CPU_ROM_TABLE_FPB_FPB_S 1
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// Field: [0] FPB_PRESENT
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//
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// 0: FPB is not present
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// 1: FPB is present.
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#define CPU_ROM_TABLE_FPB_FPB_PRESENT 0x00000001
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#define CPU_ROM_TABLE_FPB_FPB_PRESENT_BITN 0
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#define CPU_ROM_TABLE_FPB_FPB_PRESENT_M 0x00000001
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#define CPU_ROM_TABLE_FPB_FPB_PRESENT_S 0
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//*****************************************************************************
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//
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// Register: CPU_ROM_TABLE_O_ITM
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//
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//*****************************************************************************
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// Field: [31:1] ITM
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//
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// Points to the Instrumentation Trace block at 0xE0000000.
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// (2*ITM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0000000.
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#define CPU_ROM_TABLE_ITM_ITM_W 31
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#define CPU_ROM_TABLE_ITM_ITM_M 0xFFFFFFFE
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#define CPU_ROM_TABLE_ITM_ITM_S 1
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// Field: [0] ITM_PRESENT
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//
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// 0: ITM is not present
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// 1: ITM is present.
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#define CPU_ROM_TABLE_ITM_ITM_PRESENT 0x00000001
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#define CPU_ROM_TABLE_ITM_ITM_PRESENT_BITN 0
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#define CPU_ROM_TABLE_ITM_ITM_PRESENT_M 0x00000001
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#define CPU_ROM_TABLE_ITM_ITM_PRESENT_S 0
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//*****************************************************************************
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//
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// Register: CPU_ROM_TABLE_O_TPIU
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//
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//*****************************************************************************
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// Field: [31:1] TPIU
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//
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// Points to the TPIU. TPIU is at 0xE0040000.
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// (2*TPIU + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0040000.
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#define CPU_ROM_TABLE_TPIU_TPIU_W 31
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#define CPU_ROM_TABLE_TPIU_TPIU_M 0xFFFFFFFE
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#define CPU_ROM_TABLE_TPIU_TPIU_S 1
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// Field: [0] TPIU_PRESENT
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//
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// 0: TPIU is not present
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// 1: TPIU is present.
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#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT 0x00000001
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#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_BITN 0
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#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_M 0x00000001
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#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_S 0
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//*****************************************************************************
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//
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// Register: CPU_ROM_TABLE_O_ETM
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//
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//*****************************************************************************
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// Field: [31:1] ETM
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//
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// Points to the ETM. ETM is at 0xE0041000.
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// (2*ETM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0041000.
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#define CPU_ROM_TABLE_ETM_ETM_W 31
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#define CPU_ROM_TABLE_ETM_ETM_M 0xFFFFFFFE
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#define CPU_ROM_TABLE_ETM_ETM_S 1
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// Field: [0] ETM_PRESENT
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//
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// 0: ETM is not present
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// 1: ETM is present.
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#define CPU_ROM_TABLE_ETM_ETM_PRESENT 0x00000001
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#define CPU_ROM_TABLE_ETM_ETM_PRESENT_BITN 0
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#define CPU_ROM_TABLE_ETM_ETM_PRESENT_M 0x00000001
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#define CPU_ROM_TABLE_ETM_ETM_PRESENT_S 0
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//*****************************************************************************
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//
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// Register: CPU_ROM_TABLE_O_END
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//
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//*****************************************************************************
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// Field: [31:0] END
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//
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// End of the ROM table
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#define CPU_ROM_TABLE_END_END_W 32
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#define CPU_ROM_TABLE_END_END_M 0xFFFFFFFF
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#define CPU_ROM_TABLE_END_END_S 0
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//*****************************************************************************
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//
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// Register: CPU_ROM_TABLE_O_SYSTEM_ACCESS
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//
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//*****************************************************************************
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// Field: [0] SYSTEM_ACCESS
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//
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// 1: The system memory map is accessible using the DAP
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// 0: Only debug resources are accessible using the DAP
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#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS 0x00000001
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#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_BITN 0
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#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_M 0x00000001
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#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_S 0
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#endif // __CPU_ROM_TABLE__
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