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482 lines
24 KiB
C
482 lines
24 KiB
C
/******************************************************************************
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* Filename: hw_adi_3_refsys_h
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* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017)
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* Revision: 48345
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_ADI_3_REFSYS_H__
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#define __HW_ADI_3_REFSYS_H__
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//*****************************************************************************
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//
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// This section defines the register offsets of
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// ADI_3_REFSYS component
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//
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//*****************************************************************************
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// Analog Test Control
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#define ADI_3_REFSYS_O_SPARE0 0x00000001
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// Internal
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#define ADI_3_REFSYS_O_REFSYSCTL0 0x00000002
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// Internal
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#define ADI_3_REFSYS_O_REFSYSCTL1 0x00000003
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// Internal
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#define ADI_3_REFSYS_O_REFSYSCTL2 0x00000004
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// Internal
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#define ADI_3_REFSYS_O_REFSYSCTL3 0x00000005
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// DCDC Control 0
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#define ADI_3_REFSYS_O_DCDCCTL0 0x00000006
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// DCDC Control 1
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#define ADI_3_REFSYS_O_DCDCCTL1 0x00000007
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// DCDC Control 2
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#define ADI_3_REFSYS_O_DCDCCTL2 0x00000008
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// DCDC Control 3
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#define ADI_3_REFSYS_O_DCDCCTL3 0x00000009
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// Internal
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#define ADI_3_REFSYS_O_DCDCCTL4 0x0000000A
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// Internal
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#define ADI_3_REFSYS_O_DCDCCTL5 0x0000000B
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//*****************************************************************************
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//
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// Register: ADI_3_REFSYS_O_SPARE0
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//
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//*****************************************************************************
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// Field: [7:0] SPARE0
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//
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// Software should not rely on the value of a reserved. Writing any other value
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// than the reset value may result in undefined behavior.
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#define ADI_3_REFSYS_SPARE0_SPARE0_W 8
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#define ADI_3_REFSYS_SPARE0_SPARE0_M 0x000000FF
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#define ADI_3_REFSYS_SPARE0_SPARE0_S 0
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//*****************************************************************************
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//
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// Register: ADI_3_REFSYS_O_REFSYSCTL0
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//
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//*****************************************************************************
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// Field: [7:0] TESTCTL
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//
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// Internal. Only to be used through TI provided API.
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// ENUMs:
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// BMCOMPOUT Internal. Only to be used through TI provided API.
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// VTEMP Internal. Only to be used through TI provided API.
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// VREF0P8V Internal. Only to be used through TI provided API.
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// VBGUNBUFF Internal. Only to be used through TI provided API.
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// VBG Internal. Only to be used through TI provided API.
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// IREF4U Internal. Only to be used through TI provided API.
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// IVREF4U Internal. Only to be used through TI provided API.
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// IPTAT2U Internal. Only to be used through TI provided API.
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// NC Internal. Only to be used through TI provided API.
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#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_W 8
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#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_M 0x000000FF
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#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_S 0
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#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT 0x00000080
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#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP 0x00000040
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#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V 0x00000020
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#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBGUNBUFF 0x00000010
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#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBG 0x00000008
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#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IREF4U 0x00000004
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#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IVREF4U 0x00000002
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#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IPTAT2U 0x00000001
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#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC 0x00000000
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//*****************************************************************************
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//
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// Register: ADI_3_REFSYS_O_REFSYSCTL1
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//
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//*****************************************************************************
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// Field: [7:3] TRIM_VDDS_BOD
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//
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// Internal. Only to be used through TI provided API.
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// ENUMs:
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// POS_27 Internal. Only to be used through TI provided API.
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// POS_26 Internal. Only to be used through TI provided API.
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// POS_25 Internal. Only to be used through TI provided API.
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// POS_24 Internal. Only to be used through TI provided API.
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// POS_31 Internal. Only to be used through TI provided API.
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// POS_30 Internal. Only to be used through TI provided API.
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// POS_29 Internal. Only to be used through TI provided API.
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// POS_28 Internal. Only to be used through TI provided API.
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// POS_19 Internal. Only to be used through TI provided API.
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// POS_18 Internal. Only to be used through TI provided API.
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// POS_17 Internal. Only to be used through TI provided API.
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// POS_16 Internal. Only to be used through TI provided API.
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// POS_23 Internal. Only to be used through TI provided API.
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// POS_22 Internal. Only to be used through TI provided API.
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// POS_21 Internal. Only to be used through TI provided API.
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// POS_20 Internal. Only to be used through TI provided API.
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// POS_11 Internal. Only to be used through TI provided API.
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// POS_10 Internal. Only to be used through TI provided API.
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// POS_9 Internal. Only to be used through TI provided API.
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// POS_8 Internal. Only to be used through TI provided API.
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// POS_15 Internal. Only to be used through TI provided API.
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// POS_14 Internal. Only to be used through TI provided API.
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// POS_13 Internal. Only to be used through TI provided API.
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// POS_12 Internal. Only to be used through TI provided API.
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// POS_3 Internal. Only to be used through TI provided API.
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// POS_2 Internal. Only to be used through TI provided API.
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// POS_1 Internal. Only to be used through TI provided API.
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// POS_0 Internal. Only to be used through TI provided API.
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// POS_7 Internal. Only to be used through TI provided API.
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// POS_6 Internal. Only to be used through TI provided API.
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// POS_5 Internal. Only to be used through TI provided API.
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// POS_4 Internal. Only to be used through TI provided API.
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_W 5
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M 0x000000F8
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S 3
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 0x000000F8
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 0x000000F0
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_25 0x000000E8
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_24 0x000000E0
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 0x000000D8
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_30 0x000000D0
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_29 0x000000C8
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_28 0x000000C0
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_19 0x000000B8
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_18 0x000000B0
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_17 0x000000A8
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_16 0x000000A0
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_23 0x00000098
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_22 0x00000090
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_21 0x00000088
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_20 0x00000080
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_11 0x00000078
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_10 0x00000070
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_9 0x00000068
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_8 0x00000060
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_15 0x00000058
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_14 0x00000050
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_13 0x00000048
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_12 0x00000040
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_3 0x00000038
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_2 0x00000030
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_1 0x00000028
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_0 0x00000020
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_7 0x00000018
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_6 0x00000010
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_5 0x00000008
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#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_4 0x00000000
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// Field: [2] BATMON_COMP_TEST_EN
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//
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// Internal. Only to be used through TI provided API.
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// ENUMs:
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// EN Internal. Only to be used through TI provided API.
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// DIS Internal. Only to be used through TI provided API.
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#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN 0x00000004
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#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_M 0x00000004
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#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_S 2
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#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_EN 0x00000004
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#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_DIS 0x00000000
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// Field: [1:0] TESTCTL
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//
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// Internal. Only to be used through TI provided API.
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// ENUMs:
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// IPTAT1U Internal. Only to be used through TI provided API.
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// BMCOMPIN Internal. Only to be used through TI provided API.
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// NC Internal. Only to be used through TI provided API.
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#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_W 2
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#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_M 0x00000003
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#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_S 0
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#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_IPTAT1U 0x00000002
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#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_BMCOMPIN 0x00000001
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#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_NC 0x00000000
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//*****************************************************************************
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//
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// Register: ADI_3_REFSYS_O_REFSYSCTL2
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//
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//*****************************************************************************
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// Field: [7:4] TRIM_VREF
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//
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// Internal. Only to be used through TI provided API.
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#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_W 4
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#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M 0x000000F0
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#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S 4
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// Field: [1:0] TRIM_TSENSE
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//
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// Internal. Only to be used through TI provided API.
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#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_W 2
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#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_M 0x00000003
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#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_S 0
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//*****************************************************************************
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//
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// Register: ADI_3_REFSYS_O_REFSYSCTL3
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//
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//*****************************************************************************
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// Field: [7] BOD_BG_TRIM_EN
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//
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// Internal. Only to be used through TI provided API.
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#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN 0x00000080
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#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_M 0x00000080
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#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_S 7
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// Field: [6] VTEMP_EN
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//
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// Internal. Only to be used through TI provided API.
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// ENUMs:
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// EN Internal. Only to be used through TI provided API.
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// DIS Internal. Only to be used through TI provided API.
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#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN 0x00000040
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#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_M 0x00000040
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#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_S 6
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#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_EN 0x00000040
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#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_DIS 0x00000000
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// Field: [5:0] TRIM_VBG
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//
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// Internal. Only to be used through TI provided API.
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#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W 6
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#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M 0x0000003F
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#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S 0
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//*****************************************************************************
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//
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// Register: ADI_3_REFSYS_O_DCDCCTL0
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//
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//*****************************************************************************
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// Field: [7:5] GLDO_ISRC
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//
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// Set charge and re-charge current level.
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// 2's complement encoding.
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//
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// 0x0: Default 11mA.
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// 0x3: Max 15mA.
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// 0x4: Max 5mA
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#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_W 3
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#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_M 0x000000E0
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#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_S 5
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// Field: [4:0] VDDR_TRIM
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//
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// Set the VDDR voltage.
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// Proprietary encoding.
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//
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// Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15.
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// Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16.
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// Step size = 16mV
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//
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// 0x00: Default, about 1.63V.
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// 0x05: Typical voltage after trim voltage 1.71V.
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// 0x15: Max voltage 1.96V.
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// 0x16: Min voltage 1.47V.
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#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_W 5
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#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M 0x0000001F
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#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S 0
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//*****************************************************************************
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//
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// Register: ADI_3_REFSYS_O_DCDCCTL1
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//
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//*****************************************************************************
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// Field: [7:6] IPTAT_TRIM
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//
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// Trim GLDO bias current.
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// Proprietary encoding.
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//
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// 0x0: Default
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// 0x1: Increase GLDO bias by 1.3x.
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// 0x2: Increase GLDO bias by 1.6x.
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// 0x3: Decrease GLDO bias by 0.7x.
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#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_W 2
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#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_M 0x000000C0
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#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_S 6
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// Field: [5] VDDR_OK_HYST
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//
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// Increase the hysteresis for when VDDR is considered ok.
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//
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// 0: Hysteresis = 60mV
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// 1: Hysteresis = 70mV
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#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST 0x00000020
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#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_M 0x00000020
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#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_S 5
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// Field: [4:0] VDDR_TRIM_SLEEP
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//
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// Set the min VDDR voltage threshold during sleep mode.
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// Proprietary encoding.
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//
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// Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15.
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// Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16.
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// Step size = 16mV
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//
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// 0x00: Default, about 1.63V.
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// 0x19: Typical voltage after trim voltage 1.52V.
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// 0x15: Max voltage 1.96V.
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// 0x16: Min voltage 1.47V.
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#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_W 5
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#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M 0x0000001F
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#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S 0
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//*****************************************************************************
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//
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// Register: ADI_3_REFSYS_O_DCDCCTL2
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//
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//*****************************************************************************
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// Field: [6] TURNON_EA_SW
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//
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// Turn on erroramp switch
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//
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// 0: Erroramp Off (Default)
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// 1: Erroramp On. Turns on GLDO error amp switch.
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#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW 0x00000040
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#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_M 0x00000040
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#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_S 6
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// Field: [5] TEST_VDDR
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//
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// Connect VDDR to ATEST bus
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//
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// 0: Not connected.
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// 1: Connected
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//
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// Set TESTSEL = 0x0 first before setting this bit.
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#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR 0x00000020
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#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_M 0x00000020
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#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_S 5
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|
|
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// Field: [4] BIAS_DIS
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//
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// Disable dummy bias current.
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//
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// 0: Dummy bias current on (Default)
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// 1: Dummy bias current off
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#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS 0x00000010
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#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_M 0x00000010
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#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_S 4
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// Field: [3:0] TESTSEL
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//
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// Select signal for test bus, one hot.
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// ENUMs:
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// VDDROK VDDR_OK connected to test bus.
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// IB1U 1uA bias current connected to test bus.
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// PASSGATE Pass transistor gate voltage connected to test
|
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// bus.
|
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// ERRAMP_OUT Error amp output voltage connected to test bus.
|
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// NC No signal connected to test bus.
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#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_W 4
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#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_M 0x0000000F
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#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_S 0
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#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_VDDROK 0x00000008
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#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_IB1U 0x00000004
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|
#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE 0x00000002
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|
#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_ERRAMP_OUT 0x00000001
|
|
#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_NC 0x00000000
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Register: ADI_3_REFSYS_O_DCDCCTL3
|
|
//
|
|
//*****************************************************************************
|
|
//*****************************************************************************
|
|
//
|
|
// Register: ADI_3_REFSYS_O_DCDCCTL4
|
|
//
|
|
//*****************************************************************************
|
|
// Field: [7:6] DEADTIME_TRIM
|
|
//
|
|
// Internal. Only to be used through TI provided API.
|
|
#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_W 2
|
|
#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_M 0x000000C0
|
|
#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_S 6
|
|
|
|
// Field: [5:3] LOW_EN_SEL
|
|
//
|
|
// Internal. Only to be used through TI provided API.
|
|
#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_W 3
|
|
#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_M 0x00000038
|
|
#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_S 3
|
|
|
|
// Field: [2:0] HIGH_EN_SEL
|
|
//
|
|
// Internal. Only to be used through TI provided API.
|
|
#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_W 3
|
|
#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_M 0x00000007
|
|
#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_S 0
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Register: ADI_3_REFSYS_O_DCDCCTL5
|
|
//
|
|
//*****************************************************************************
|
|
// Field: [5] TESTN
|
|
//
|
|
// Internal. Only to be used through TI provided API.
|
|
#define ADI_3_REFSYS_DCDCCTL5_TESTN 0x00000020
|
|
#define ADI_3_REFSYS_DCDCCTL5_TESTN_M 0x00000020
|
|
#define ADI_3_REFSYS_DCDCCTL5_TESTN_S 5
|
|
|
|
// Field: [4] TESTP
|
|
//
|
|
// Internal. Only to be used through TI provided API.
|
|
#define ADI_3_REFSYS_DCDCCTL5_TESTP 0x00000010
|
|
#define ADI_3_REFSYS_DCDCCTL5_TESTP_M 0x00000010
|
|
#define ADI_3_REFSYS_DCDCCTL5_TESTP_S 4
|
|
|
|
// Field: [3] DITHER_EN
|
|
//
|
|
// Internal. Only to be used through TI provided API.
|
|
// ENUMs:
|
|
// EN Internal. Only to be used through TI provided API.
|
|
// DIS Internal. Only to be used through TI provided API.
|
|
#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN 0x00000008
|
|
#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_M 0x00000008
|
|
#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_S 3
|
|
#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_EN 0x00000008
|
|
#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_DIS 0x00000000
|
|
|
|
// Field: [2:0] IPEAK
|
|
//
|
|
// Internal. Only to be used through TI provided API.
|
|
#define ADI_3_REFSYS_DCDCCTL5_IPEAK_W 3
|
|
#define ADI_3_REFSYS_DCDCCTL5_IPEAK_M 0x00000007
|
|
#define ADI_3_REFSYS_DCDCCTL5_IPEAK_S 0
|
|
|
|
|
|
#endif // __ADI_3_REFSYS__
|