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81 lines
2.1 KiB
C
81 lines
2.1 KiB
C
/*
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* Copyright (C) 2018 Mesotic SAS
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_saml1x
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* @{
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*
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* @file cpu.c
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* @brief Implementation of the CPU initialization for Microchip
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* SAML10/SAML11 MCUs
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*
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* @author Dylan Laduranty <dylan.laduranty@mesotic.com>
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* @}
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*/
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#include "cpu.h"
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#include "periph/init.h"
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#include "board.h"
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#ifdef CPU_FAM_SAML11
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#define _NVMCTRL NVMCTRL_SEC
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#else
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#define _NVMCTRL NVMCTRL
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#endif
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static void _gclk_setup(int gclk, uint32_t reg)
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{
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GCLK->GENCTRL[gclk].reg = reg;
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while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(gclk)) {}
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}
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/**
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* @brief Initialize the CPU, set IRQ priorities, clocks
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*/
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void cpu_init(void)
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{
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/* initialize the Cortex-M core */
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cortexm_init();
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/* turn on only needed APB peripherals */
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MCLK->APBAMASK.reg = MCLK_APBAMASK_MCLK
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| MCLK_APBAMASK_OSCCTRL
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| MCLK_APBAMASK_GCLK
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| MCLK_APBAMASK_PM
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#ifdef MODULE_PERIPH_GPIO_IRQ
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| MCLK_APBAMASK_EIC
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#endif
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#ifdef MODULE_PERIPH_GPIO
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| MCLK_APBAMASK_PORT
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#endif
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;
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/* Software reset the GCLK module to ensure it is re-initialized correctly */
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GCLK->CTRLA.reg = GCLK_CTRLA_SWRST;
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while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) {}
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while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) {}
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PM->PLCFG.reg = PM_PLCFG_PLSEL_PL2;
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while (0 == PM->INTFLAG.bit.PLRDY) {}
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MCLK->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL;
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_NVMCTRL->CTRLB.reg |= NVMCTRL_CTRLB_RWS(1);
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MCLK->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL;
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/* set OSC16M to 16MHz */
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OSCCTRL->OSC16MCTRL.bit.FSEL = 3;
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OSCCTRL->OSC16MCTRL.bit.ONDEMAND = 0;
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OSCCTRL->OSC16MCTRL.bit.RUNSTDBY = 0;
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/* Setup GCLK generators */
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_gclk_setup(0, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M);
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/* trigger static peripheral initialization */
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periph_init();
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}
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