Steffen Pengel 35635e4039 stm32f3: periph: uart: add misssing uart overrun handling ... On overrung the ORE bit in the ORECF register is set. An overrun error occurs when a character is received when RXNE has not been reset. Data can not be transferred from the shift register to the RDR register until the RXNE bit is cleared. The ORE bit is reset by setting the ORECF bit in the ICR register. In case the ORE bit isn't cleared, the isr_handler() routine is called continuously. Which prevents the system from normal scheduling.		2016-02-21 20:30:29 +01:00
..
include	cpu/stm32: use common CPUID implementation	2016-02-10 09:12:30 +01:00
ldscripts	cpu/stm32: use common CPUID implementation	2016-02-10 09:12:30 +01:00
periph	stm32f3: periph: uart: add misssing uart overrun handling	2016-02-21 20:30:29 +01:00
cpu.c	cpu/stm32f3: adapted to centralized cpu conf	2015-05-29 16:44:52 +02:00
lpm_arch.c	cpu: Initial import of stm32f3	2014-07-31 19:38:26 +02:00
Makefile	cpu/stm32f3: use common STM32 files	2016-02-10 09:12:29 +01:00
Makefile.include	cpu/stm32f3: use common STM32 files	2016-02-10 09:12:29 +01:00
vectors.c	cpu/stm32f3: optimization of startup code	2015-06-15 16:00:51 +02:00