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https://github.com/RIOT-OS/RIOT.git
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140 lines
5.4 KiB
C
140 lines
5.4 KiB
C
/*
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* Copyright (C) 2018 Mesotic SAS
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_saml1x
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* @brief CPU specific definitions for internal peripheral handling
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author Dylan Laduranty <dylan.laduranty@mesotic.com>
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*/
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#ifndef PERIPH_CPU_H
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#define PERIPH_CPU_H
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#include "periph_cpu_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Power mode configuration
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* @{
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*/
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#define PM_NUM_MODES (2)
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/** @} */
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/**
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* @name SAML1x GCLK definitions
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* @{
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*/
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enum {
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SAM0_GCLK_MAIN = 0, /**< 16 MHz main clock */
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SAM0_GCLK_32KHZ, /**< 32 kHz clock */
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};
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/** @} */
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#ifndef DOXYGEN
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#define HAVE_ADC_RES_T
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typedef enum {
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ADC_RES_6BIT = 0xff, /**< not supported */
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ADC_RES_8BIT = ADC_CTRLC_RESSEL_8BIT, /**< ADC resolution: 8 bit */
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ADC_RES_10BIT = ADC_CTRLC_RESSEL_10BIT, /**< ADC resolution: 10 bit */
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ADC_RES_12BIT = ADC_CTRLC_RESSEL_12BIT, /**< ADC resolution: 12 bit */
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ADC_RES_14BIT = 0xfe, /**< not supported */
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ADC_RES_16BIT = 0xfd /**< not supported */
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} adc_res_t;
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#endif /* ndef DOXYGEN */
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/**
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* @brief The MCU has a 10 bit DAC
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*/
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#define DAC_RES_BITS (10)
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/**
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* @brief The MCU has one DAC Output.
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*/
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#define DAC_NUMOF (1)
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/**
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* @name Real time counter configuration
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* @{
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*/
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#define RTT_MAX_VALUE (0xffffffff)
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#define RTT_CLOCK_FREQUENCY (32768U) /* in Hz */
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#define RTT_MIN_FREQUENCY (RTT_CLOCK_FREQUENCY / 1024U) /* in Hz */
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#define RTT_MAX_FREQUENCY (RTT_CLOCK_FREQUENCY) /* in Hz */
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/** @} */
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/**
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* @brief RTC input pins that can be used for tamper detection and
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* wake from Deep Sleep
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*/
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static const gpio_t rtc_tamper_pins[RTC_NUM_OF_TAMPERS] = {
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GPIO_PIN(PA, 8), GPIO_PIN(PA, 9), GPIO_PIN(PA, 16),
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GPIO_PIN(PA, 17)
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};
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/**
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* @brief NVM User Row Mapping - Dedicated Entries
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* Config values will be applied at power-on.
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*/
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struct sam0_aux_cfg_mapping {
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/* config word 0 */
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uint32_t secure_region_unlock : 3; /**< NVM Secure Region UnLock Bits */
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uint32_t non_secure_region_unlock : 3; /**< NVM Non-Secure Region UnLock Bits */
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uint32_t reserved_0 : 1; /**< Reserved */
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uint32_t bod33_level : 6; /**< BOD33 threshold level at power-on. */
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uint32_t bod33_disable : 1; /**< BOD33 Disable at power-on. */
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uint32_t bod33_action : 2; /**< BOD33 Action at power-on. */
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const uint32_t bod12_calibration : 9; /**< Factory settings - do not change. */
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uint32_t wdt_run_standby : 1; /**< WDT Runstdby at power-on */
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uint32_t wdt_enable : 1; /**< WDT Enable at power-on. */
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uint32_t wdt_always_on : 1; /**< WDT Always-On at power-on. */
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uint32_t wdt_period : 4; /**< WDT Period at power-on. */
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/* config word 1 */
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uint32_t wdt_window : 4; /**< WDT Window at power-on. */
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uint32_t wdt_ewoffset : 4; /**< WDT Early Warning Interrupt Offset */
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uint32_t wdt_window_enable : 1; /**< WDT Window mode enabled on power-on */
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uint32_t bod33_hysteresis : 1; /**< BOD33 Hysteresis configuration */
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uint32_t reserved_1 : 1; /**< Reserved */
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uint32_t ram_execute_never : 1; /**< RAM is eXecute Never */
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uint32_t data_execute_never : 1; /**< Data Flash is eXecute Never */
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uint32_t reserved_2 : 19; /**< Reserved */
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/* config word 2 */
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uint32_t secure_flash_as_size : 8; /**< Secure Flash (AS region) Size = AS*0x100 */
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uint32_t nsc_size : 6; /**< Non-Secure Callable Flash (APPLICATION region) Size = ANSC*0x20 */
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uint32_t reserved_3 : 2; /**< Reserved */
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uint32_t secure_flash_data_size : 4; /**< Secure Data Flash Size = DS*0x100 */
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uint32_t reserved_4 : 4; /**< Reserved */
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uint32_t secure_ram_size : 7; /**< Secure SRAM Size = RS*0x80 */
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uint32_t reserved_5 : 1; /**< Reserved */
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/* config word 3 */
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uint32_t user_row_write_enable : 1; /**< User Row Write Enable */
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uint32_t reserved_6 : 31; /**< Reserved */
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/* config word 4 */
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uint32_t nonsec_a; /**< Peripherals Non-Secure Status Fuses for Bridge A */
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/* config word 5 */
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uint32_t nonsec_b; /**< Peripherals Non-Secure Status Fuses for Bridge B */
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/* config word 6 */
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uint32_t nonsec_c; /**< Peripherals Non-Secure Status Fuses for Bridge C */
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/* config word 7 */
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uint32_t user_crc; /**< CRC of NVM User Row bits 223:64 (words 2…6) */
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_H */
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/** @} */
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