mirror of
https://github.com/RIOT-OS/RIOT.git
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400 lines
8.6 KiB
C
400 lines
8.6 KiB
C
/*
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* Copyright (C) 2019 ML!PA Consulting GmbH
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*
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_sam0_common
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* @ingroup drivers_periph_timer
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* @{
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*
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* @file timer.c
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* @brief Low-level timer driver implementation
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*
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* @author Benjamin Valentin <benjamin.valentin@ml-pa.com>
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*
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* @}
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*/
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#include <assert.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include "board.h"
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#include "cpu.h"
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#include "periph/timer.h"
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#include "periph_conf.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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/**
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* @brief Timer state memory
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*/
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static timer_isr_ctx_t config[TIMER_NUMOF];
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static uint32_t _oneshot;
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static inline void set_oneshot(tim_t tim, int chan)
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{
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_oneshot |= (1 << chan) << (TIMER_CHANNEL_NUMOF * tim);
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}
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static inline void clear_oneshot(tim_t tim, int chan)
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{
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_oneshot &= ~((1 << chan) << (TIMER_CHANNEL_NUMOF * tim));
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}
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static inline bool is_oneshot(tim_t tim, int chan)
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{
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return _oneshot & ((1 << chan) << (TIMER_CHANNEL_NUMOF * tim));
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}
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static inline TcCount32 *dev(tim_t tim)
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{
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return &timer_config[tim].dev->COUNT32;
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}
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static inline TcCount16 *dev16(tim_t tim)
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{
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return &timer_config[tim].dev->COUNT16;
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}
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static inline TcCount8 *dev8(tim_t tim)
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{
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return &timer_config[tim].dev->COUNT8;
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}
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static inline void wait_synchronization(tim_t tim)
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{
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#if defined(TC_SYNCBUSY_MASK)
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/* SYNCBUSY is a register */
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while ((dev(tim)->SYNCBUSY.reg) != 0) {}
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#elif defined(TC_STATUS_SYNCBUSY)
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/* SYNCBUSY is a bit */
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while ((dev(tim)->STATUS.reg & TC_STATUS_SYNCBUSY) != 0) {}
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#else
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#error Unsupported device
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#endif
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}
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/* enable timer interrupts */
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static inline void _irq_enable(tim_t tim)
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{
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NVIC_EnableIRQ(timer_config[tim].irq);
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}
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static uint8_t _get_prescaler(uint32_t freq_out, uint32_t freq_in)
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{
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uint8_t scale = 0;
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while (freq_in > freq_out) {
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freq_in >>= 1;
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/* after DIV16 the prescaler gets more coarse */
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if (++scale > TC_CTRLA_PRESCALER_DIV16_Val) {
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freq_in >>= 1;
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}
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}
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/* fail if output frequency can't be derived from input frequency */
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assert(freq_in == freq_out);
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return scale;
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}
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/* TOP value is CC0 */
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static inline void _set_mfrq(tim_t tim)
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{
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#ifdef TC_WAVE_WAVEGEN_MFRQ
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dev(tim)->WAVE.reg = TC_WAVE_WAVEGEN_MFRQ;
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#else
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dev(tim)->CTRLA.bit.WAVEGEN = TC_CTRLA_WAVEGEN_MFRQ_Val;
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#endif
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}
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/* TOP value is MAX timer value */
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static inline void _set_nfrq(tim_t tim)
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{
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#ifdef TC_WAVE_WAVEGEN_NFRQ
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dev(tim)->WAVE.reg = TC_WAVE_WAVEGEN_NFRQ;
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#else
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dev(tim)->CTRLA.bit.WAVEGEN = TC_CTRLA_WAVEGEN_NFRQ_Val;
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#endif
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}
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/**
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* @brief Setup the given timer
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*/
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int timer_init(tim_t tim, uint32_t freq, timer_cb_t cb, void *arg)
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{
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const tc32_conf_t *cfg = &timer_config[tim];
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uint8_t scale = _get_prescaler(freq, sam0_gclk_freq(cfg->gclk_src));
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/* make sure given device is valid */
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if (tim >= TIMER_NUMOF) {
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return -1;
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}
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/* make sure the prescaler is within range */
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if (scale > TC_CTRLA_PRESCALER_DIV1024_Val) {
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DEBUG("[timer %d] scale %d is out of range\n", tim, scale);
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return -1;
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}
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/* make sure the timer is not running */
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timer_stop(tim);
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sam0_gclk_enable(cfg->gclk_src);
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#ifdef MCLK
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GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_GEN(cfg->gclk_src) | GCLK_PCHCTRL_CHEN;
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*cfg->mclk |= cfg->mclk_mask;
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#else
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(cfg->gclk_src) | cfg->gclk_ctrl;
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PM->APBCMASK.reg |= cfg->pm_mask;
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#endif
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/* reset the timer */
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dev(tim)->CTRLA.bit.SWRST = 1;
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while (dev(tim)->CTRLA.bit.SWRST) {}
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dev(tim)->CTRLA.reg = cfg->flags
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#ifdef TC_CTRLA_WAVEGEN_NFRQ
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| TC_CTRLA_WAVEGEN_NFRQ
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#endif
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| TC_CTRLA_PRESCALER(scale)
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| TC_CTRLA_PRESCSYNC_RESYNC;
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#ifdef TC_WAVE_WAVEGEN_NFRQ
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dev(tim)->WAVE.reg = TC_WAVE_WAVEGEN_NFRQ;
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#endif
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wait_synchronization(tim);
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dev(tim)->INTENCLR.reg = TC_INTENCLR_MASK;
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/* save callback */
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config[tim].cb = cb;
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config[tim].arg = arg;
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timer_start(tim);
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/* enable interrupts for given timer */
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_irq_enable(tim);
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return 0;
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}
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static void _set_cc(tim_t tim, int cc, unsigned int value)
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{
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const uint16_t flags = timer_config[tim].flags;
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if (flags & TC_CTRLA_MODE_COUNT32) {
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dev(tim)->CC[cc].reg = value;
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return;
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}
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if (flags & TC_CTRLA_MODE_COUNT8) {
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dev8(tim)->CC[cc].reg = value;
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return;
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}
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/* 16 bit is the default */
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dev16(tim)->CC[cc].reg = value;
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}
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int timer_set_absolute(tim_t tim, int channel, unsigned int value)
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{
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DEBUG("Setting timer %i channel %i to %i\n", tim, channel, value);
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/* set timeout value */
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switch (channel) {
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case 0:
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dev(tim)->INTFLAG.reg = TC_INTFLAG_MC0;
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_set_cc(tim, 0, value);
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dev(tim)->INTENSET.reg = TC_INTENSET_MC0;
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break;
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case 1:
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dev(tim)->INTFLAG.reg = TC_INTFLAG_MC1;
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_set_cc(tim, 1, value);
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dev(tim)->INTENSET.reg = TC_INTENSET_MC1;
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break;
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default:
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return -1;
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}
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set_oneshot(tim, channel);
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return 0;
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}
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int timer_set_periodic(tim_t tim, int channel, unsigned int value, uint8_t flags)
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{
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DEBUG("Setting timer %i channel %i to %i (repeating)\n", tim, channel, value);
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timer_stop(tim);
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/* set timeout value */
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switch (channel) {
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case 0:
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/* clear interrupt */
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dev(tim)->INTFLAG.reg = TC_INTFLAG_MC0;
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if (flags & TIM_FLAG_RESET_ON_MATCH) {
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_set_mfrq(tim);
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} else {
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_set_nfrq(tim);
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}
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_set_cc(tim, 0, value);
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dev(tim)->INTENSET.reg = TC_INTENSET_MC0;
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break;
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case 1:
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/* only CC0 can be used to set TOP */
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if (flags & TIM_FLAG_RESET_ON_MATCH) {
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assert(0);
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return -1;
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}
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dev(tim)->INTFLAG.reg = TC_INTFLAG_MC1;
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_set_cc(tim, 1, value);
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dev(tim)->INTENSET.reg = TC_INTENSET_MC1;
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break;
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default:
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return -1;
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}
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if (flags & TIM_FLAG_RESET_ON_SET) {
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dev(tim)->COUNT.reg = 0;
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}
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if (!(flags & TIM_FLAG_SET_STOPPED)) {
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timer_start(tim);
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}
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clear_oneshot(tim, channel);
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return 0;
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}
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int timer_clear(tim_t tim, int channel)
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{
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switch (channel) {
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case 0:
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dev(tim)->INTFLAG.reg = TC_INTFLAG_MC0;
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dev(tim)->INTENCLR.reg = TC_INTENCLR_MC0;
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break;
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case 1:
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dev(tim)->INTFLAG.reg = TC_INTFLAG_MC1;
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dev(tim)->INTENCLR.reg = TC_INTENCLR_MC1;
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break;
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default:
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return -1;
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}
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return 0;
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}
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unsigned int timer_read(tim_t tim)
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{
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/* WORKAROUND to prevent being stuck there if timer not init */
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if (!dev(tim)->CTRLA.bit.ENABLE) {
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return 0;
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}
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/* request syncronisation */
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#ifdef TC_CTRLBSET_CMD_READSYNC_Val
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dev(tim)->CTRLBSET.reg = TC_CTRLBSET_CMD_READSYNC;
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/* work around a possible hardware bug where it takes some
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cycles for the timer peripheral to set the SYNCBUSY/READSYNC bit
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after writing the READSYNC bit
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The problem was observed on SAME54.
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*/
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while(dev(tim)->CTRLBSET.bit.CMD == TC_CTRLBSET_CMD_READSYNC_Val) {}
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#else
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dev(tim)->READREQ.reg = TC_READREQ_RREQ | TC_READREQ_ADDR(TC_COUNT32_COUNT_OFFSET);
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#endif
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wait_synchronization(tim);
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return dev(tim)->COUNT.reg;
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}
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void timer_stop(tim_t tim)
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{
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dev(tim)->CTRLA.bit.ENABLE = 0;
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wait_synchronization(tim);
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}
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void timer_start(tim_t tim)
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{
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wait_synchronization(tim);
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dev(tim)->CTRLA.bit.ENABLE = 1;
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}
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static inline void timer_isr(tim_t tim)
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{
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TcCount32 *tc = dev(tim);
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uint8_t status = tc->INTFLAG.reg;
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/* Acknowledge all interrupts */
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tc->INTFLAG.reg = status;
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if ((status & TC_INTFLAG_MC0) && tc->INTENSET.bit.MC0) {
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if (is_oneshot(tim, 0)) {
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tc->INTENCLR.reg = TC_INTENCLR_MC0;
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}
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if (config[tim].cb) {
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config[tim].cb(config[tim].arg, 0);
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}
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}
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if ((status & TC_INTFLAG_MC1) && tc->INTENSET.bit.MC1) {
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if (is_oneshot(tim, 1)) {
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tc->INTENCLR.reg = TC_INTENCLR_MC1;
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}
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if (config[tim].cb) {
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config[tim].cb(config[tim].arg, 1);
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}
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}
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}
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#ifdef TIMER_0_ISR
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void TIMER_0_ISR(void)
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{
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timer_isr(0);
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cortexm_isr_end();
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}
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#endif
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#ifdef TIMER_1_ISR
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void TIMER_1_ISR(void)
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{
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timer_isr(1);
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cortexm_isr_end();
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}
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#endif
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#ifdef TIMER_2_ISR
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void TIMER_2_ISR(void)
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{
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timer_isr(2);
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cortexm_isr_end();
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}
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#endif
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#ifdef TIMER_3_ISR
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void TIMER_3_ISR(void)
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{
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timer_isr(3);
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cortexm_isr_end();
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}
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#endif
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