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4acceefa65
- Since the Vector table must be naturally aligned to the next power of two of the amount of supported ISR, and the table will be placed after riotboot_hdr, we must ensure RIOTBOOT_HRD_LEN has the same alignment.
66 lines
3.1 KiB
Makefile
66 lines
3.1 KiB
Makefile
# include module specific includes
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INCLUDES += -I$(RIOTCPU)/cortexm_common/include
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INCLUDES += -I$(RIOTCPU)/cortexm_common/include/vendor
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# All variables must be defined in the CPU configuration when using the common
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# `ldscripts/cortexm.ld`
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ifneq (,$(ROM_START_ADDR)$(RAM_START_ADDR)$(ROM_LEN)$(RAM_LEN))
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$(if $(ROM_START_ADDR),,$(error ROM_START_ADDR is not defined))
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$(if $(RAM_START_ADDR),,$(error RAM_START_ADDR is not defined))
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$(if $(ROM_LEN),,$(error ROM_LEN is not defined))
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$(if $(RAM_LEN),,$(error RAM_LEN is not defined))
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LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_rom_start_addr=$(ROM_START_ADDR)
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LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_ram_start_addr=$(RAM_START_ADDR)
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LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_rom_length=$(ROM_LEN)
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LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_ram_length=$(RAM_LEN)
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endif
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TOOLCHAINS_SUPPORTED = gnu llvm
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# Only define the linker symbol if the variable is set
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# The variable can be set using target specific variable thanks to lazy evaluation
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# ROM_OFFSET: offset in rom to start linking, allows supporting a bootloader
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LINKFLAGS += $(if $(ROM_OFFSET),$(LINKFLAGPREFIX)--defsym=_rom_offset=$(ROM_OFFSET))
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# FW_ROM_LEN: rom length to use for firmware linking. Allows linking only in a section of the rom.
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LINKFLAGS += $(if $(FW_ROM_LEN),$(LINKFLAGPREFIX)--defsym=_fw_rom_length=$(FW_ROM_LEN))
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# Cortex-M0+/1/3/4/7 riotboot settings
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# From ARMv7-M (M4, M3, M7) architecture reference manual, section B1.5.3
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# https://static.docs.arm.com/ddi0403/e/DDI0403E_d_armv7m_arm.pdf
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# "The Vector table must be naturally aligned to a power of two whose alignment
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# value is greater than or equal to number of Exceptions supported x 4"
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# From ARMv6-M (M0, M0+, M1) architecture reference manual, section B1.5.3
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# https://static.docs.arm.com/ddi0419/d/DDI0419D_armv6m_arm.pdf
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# "The table offset address that VTOR defines is 32-word aligned. Where more
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# than 16 external interrupts are used, the offset word alignment must be
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# increased to accommodate vectors for all the exceptions and interrupts
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# supported and keep the required table size naturally aligned."
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# For reference on the max number in interrupts per processor look in The
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# technical reference manual "Interrupt Controller Type Register, ICTR" section.
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# * For M4, M3 & M7: Maximum of 256 exceptions (256*4 bytes == 0x400).
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# * For M0, M0+ & M1: Maximum of 48 exceptions (48*4 bytes = 192 bytes ~= 0x100).
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# The values defined here are a theoretical maximum, in practice most cpu's
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# CPU_IRQ_NUMOF value is around 100, in these cases the value can be reduced
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# accordingly in the cpu Makefile.include, e.g: `kinetis/Makefile.include`
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ifneq (,$(filter cortex-m2% cortex-m4% cortex-m3% cortex-m7%,$(CPU_ARCH)))
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RIOTBOOT_HDR_LEN ?= 0x400
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else
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RIOTBOOT_HDR_LEN ?= 0x100
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endif
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# Configure riotboot bootloader and slot lengths
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# 4KB are currently enough
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RIOTBOOT_LEN ?= 0x1000
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# Currently 2 slots are supported by default, equals in length
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NUM_SLOTS ?= 2
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# Take the whole flash minus RIOTBOOT_LEN and divide it by NUM_SLOTS
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SLOT0_LEN ?= $(shell printf "0x%x" $$((($(ROM_LEN:%K=%*1024)-$(RIOTBOOT_LEN)) / $(NUM_SLOTS))))
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SLOT1_LEN ?= $(SLOT0_LEN)
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SLOT0_LEN := $(SLOT0_LEN)
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SLOT1_LEN := $(SLOT1_LEN)
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