mirror of
https://github.com/RIOT-OS/RIOT.git
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4a9cb807c6
The CPU has multiple issues and several parts of the platform code does not even compile cleanly for this CPU in the current state. This removes support for parts MK60DN256ZVLL10, MK60DN512ZVLL10 (note the Z) CPUs with this part number were used in Mulle v0.60 which only has been used in some in-house projects at Eistec and LTU.
255 lines
7.6 KiB
C
255 lines
7.6 KiB
C
/*
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* Copyright (C) 2015 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @defgroup cpu_k60 Freescale Kinetis K60
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* @ingroup cpu
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* @brief CPU specific implementations for the Freescale Kinetis K60
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* @{
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*
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* @file
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* @brief Implementation specific CPU configuration options
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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#ifndef CPU_CONF_H
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#define CPU_CONF_H
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#include "cpu_conf_common.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include <stdint.h>
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#if defined(CPU_MODEL_K60DN512VLL10) || defined(CPU_MODEL_K60DN256VLL10)
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#include "vendor/MK60D10.h"
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/** The expected CPUID value, can be used to implement a check that we are
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* running on the right hardware */
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#define K60_EXPECTED_CPUID 0x410fc241u
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/* K60 rev 2.x replaced the RNG module in 1.x by the RNGA PRNG module */
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#define KINETIS_RNGA (RNG)
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#else
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#error Unknown CPU model. Update Makefile.include in the board directory.
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#endif
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/**
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* @brief ARM Cortex-M specific CPU configuration
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* @{
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*/
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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#define CPU_IRQ_NUMOF (104U)
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#define CPU_FLASH_BASE (0x00000000)
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/** @} */
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/**
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* @name GPIO pin mux function numbers
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*/
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/** @{ */
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#define PIN_MUX_FUNCTION_ANALOG 0
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#define PIN_MUX_FUNCTION_GPIO 1
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/** @} */
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/**
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* @name GPIO interrupt flank settings
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*/
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/** @{ */
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#define PIN_INTERRUPT_RISING 0b1001
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#define PIN_INTERRUPT_FALLING 0b1010
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#define PIN_INTERRUPT_EDGE 0b1011
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/** @} */
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/** @name PORT module clock gates */
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/** @{ */
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#define PORTA_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT))
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#define PORTB_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT))
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#define PORTC_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT))
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#define PORTD_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT))
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#define PORTE_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT))
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/** @} */
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/**
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* @name UART driver settings
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*/
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/** @{ */
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/** UART typedef from CPU header. */
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#define KINETIS_UART UART_Type
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/** @} */
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/**
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* @name Clock settings for the LPTMR0 timer
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* @{
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*/
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#define LPTIMER_DEV (LPTMR0) /**< LPTIMER hardware module */
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#define LPTIMER_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 1) /**< Enable LPTMR0 clock gate */
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#define LPTIMER_CLKDIS() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 0) /**< Disable LPTMR0 clock gate */
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#define LPTIMER_CLKSRC_MCGIRCLK 0 /**< internal reference clock (4MHz) */
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#define LPTIMER_CLKSRC_LPO 1 /**< PMC 1kHz output */
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#define LPTIMER_CLKSRC_ERCLK32K 2 /**< RTC clock 32768Hz */
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#define LPTIMER_CLKSRC_OSCERCLK 3 /**< system oscillator output, clock from RF-Part */
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#ifndef LPTIMER_CLKSRC
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#define LPTIMER_CLKSRC LPTIMER_CLKSRC_ERCLK32K /**< default clock source */
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#endif
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#if (LPTIMER_CLKSRC == LPTIMER_CLKSRC_MCGIRCLK)
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#define LPTIMER_CLK_PRESCALE 1
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#define LPTIMER_SPEED 1000000
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#elif (LPTIMER_CLKSRC == LPTIMER_CLKSRC_OSCERCLK)
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#define LPTIMER_CLK_PRESCALE 1
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#define LPTIMER_SPEED 1000000
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#elif (LPTIMER_CLKSRC == LPTIMER_CLKSRC_ERCLK32K)
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#define LPTIMER_CLK_PRESCALE 0
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#define LPTIMER_SPEED 32768
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#else
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#define LPTIMER_CLK_PRESCALE 0
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#define LPTIMER_SPEED 1000
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#endif
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/** IRQ priority for hwtimer interrupts */
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#define LPTIMER_IRQ_PRIO 1
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/** IRQ channel for hwtimer interrupts */
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#define LPTIMER_IRQ_CHAN LPTMR0_IRQn
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/** @} */
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/**
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* @name Power mode hardware details
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*/
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/** @{ */
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#define KINETIS_PMCTRL SMC->PMCTRL
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#define KINETIS_PMCTRL_SET_MODE(x) (KINETIS_PMCTRL = SMC_PMCTRL_STOPM(x) | SMC_PMCTRL_LPWUI_MASK)
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/* Clear LLS protection, clear VLPS, VLPW, VLPR protection */
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/* Note: This register can only be written once after each reset, so we must
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* enable all power modes that we wish to use. */
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#define KINETIS_PMPROT_UNLOCK() (SMC->PMPROT |= SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK)
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/**
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* @name STOP mode bitfield values
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* @{
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*/
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/** @brief Normal STOP */
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#define KINETIS_POWER_MODE_NORMAL (0b000)
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/** @brief VLPS STOP */
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#define KINETIS_POWER_MODE_VLPS (0b010)
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/** @brief LLS STOP */
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#define KINETIS_POWER_MODE_LLS (0b011)
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/** @} */
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/**
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* @brief Wake up source number for the LPTMR0
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*
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* In order to let the hwtimer wake the CPU from low power modes, we need to
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* enable this wake up source.
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*/
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#define KINETIS_LLWU_WAKEUP_MODULE_LPTMR 0
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/**
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* @brief IRQn name to enable LLWU IRQ in NVIC
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*/
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#define KINETIS_LLWU_IRQ LLW_IRQn
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/**
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* @brief Enable clock gate on LLWU module.
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*/
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#define LLWU_UNLOCK() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_LLWU_SHIFT) = 1)
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/**
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* @brief Internal modules whose interrupts are mapped to LLWU wake up sources.
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*
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* Other modules CAN NOT be used to wake the CPU from LLS or VLLSx power modes.
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*/
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typedef enum llwu_wakeup_module {
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KINETIS_LPM_WAKEUP_MODULE_LPTMR = 0,
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KINETIS_LPM_WAKEUP_MODULE_CMP0 = 1,
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KINETIS_LPM_WAKEUP_MODULE_CMP1 = 2,
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KINETIS_LPM_WAKEUP_MODULE_CMP2 = 3,
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KINETIS_LPM_WAKEUP_MODULE_TSI = 4,
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KINETIS_LPM_WAKEUP_MODULE_RTC_ALARM = 5,
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KINETIS_LPM_WAKEUP_MODULE_RESERVED = 6,
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KINETIS_LPM_WAKEUP_MODULE_RTC_SECONDS = 7,
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KINETIS_LPM_WAKEUP_MODULE_END,
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} llwu_wakeup_module_t;
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/**
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* @brief enum that maps physical pins to wakeup pin numbers in LLWU module
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*
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* Other pins CAN NOT be used to wake the CPU from LLS or VLLSx power modes.
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*/
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typedef enum llwu_wakeup_pin {
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KINETIS_LPM_WAKEUP_PIN_PTE1 = 0,
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KINETIS_LPM_WAKEUP_PIN_PTE2 = 1,
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KINETIS_LPM_WAKEUP_PIN_PTE4 = 2,
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KINETIS_LPM_WAKEUP_PIN_PTA4 = 3,
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KINETIS_LPM_WAKEUP_PIN_PTA13 = 4,
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KINETIS_LPM_WAKEUP_PIN_PTB0 = 5,
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KINETIS_LPM_WAKEUP_PIN_PTC1 = 6,
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KINETIS_LPM_WAKEUP_PIN_PTC3 = 7,
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KINETIS_LPM_WAKEUP_PIN_PTC4 = 8,
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KINETIS_LPM_WAKEUP_PIN_PTC5 = 9,
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KINETIS_LPM_WAKEUP_PIN_PTC6 = 10,
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KINETIS_LPM_WAKEUP_PIN_PTC11 = 11,
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KINETIS_LPM_WAKEUP_PIN_PTD0 = 12,
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KINETIS_LPM_WAKEUP_PIN_PTD2 = 13,
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KINETIS_LPM_WAKEUP_PIN_PTD4 = 14,
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KINETIS_LPM_WAKEUP_PIN_PTD6 = 15,
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KINETIS_LPM_WAKEUP_PIN_END
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} llwu_wakeup_pin_t;
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/** @} */
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/**
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* @name Bit band macros
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* @{
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*/
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/* Generic bitband conversion routine */
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/** @brief Convert bit-band region address and bit number to bit-band alias address
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*
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* @param[in] addr base address in non-bit-banded memory
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* @param[in] bit bit number within the word
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*
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* @return Address of the bit within the bit-band memory region
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*/
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#define BITBAND_ADDR(addr, bit) ((((uint32_t) (addr)) & 0xF0000000u) + 0x2000000 + ((((uint32_t) (addr)) & 0xFFFFF) << 5) + ((bit) << 2))
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/**
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* @brief Bitband 32 bit access to variable stored in SRAM_U
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*
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* @note SRAM_L is not bit band aliased on the K60, only SRAM_U (0x20000000 and up)
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* @note var must be declared 'volatile'
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*/
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#define BITBAND_VAR32(var, bit) (*((uint32_t volatile*) BITBAND_ADDR(&(var), (bit))))
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/**
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* @brief Bitband 16 bit access to variable stored in SRAM_U
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*
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* @note SRAM_L is not bit band aliased on the K60, only SRAM_U (0x20000000 and up)
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* @note var must be declared 'volatile'
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*/
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#define BITBAND_VAR16(var, bit) (*((uint16_t volatile*) BITBAND_ADDR(&(var), (bit))))
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/**
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* @brief Bitband 8 bit access to variable stored in SRAM_U
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*
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* @note SRAM_L is not bit band aliased on the K60, only SRAM_U (0x20000000 and up)
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* @note var must be declared 'volatile'
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*/
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#define BITBAND_VAR8(var, bit) (*((uint8_t volatile*) BITBAND_ADDR(&(var), (bit))))
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPU_CONF_H */
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/** @} */
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