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https://github.com/RIOT-OS/RIOT.git
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145 lines
3.5 KiB
C
145 lines
3.5 KiB
C
/*
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* Copyright (C) 2017 Ken Rabold
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* 2019 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_hifive1
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* @{
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*
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* @file
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* @brief Peripheral specific definitions for the HiFive1 RISC-V board
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*
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* @author Ken Rabold
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Core Clock configuration
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* @{
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*/
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#define USE_CLOCK_HFXOSC_PLL (1)
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#define USE_CLOCK_HFXOSC (0)
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#define USE_CLOCK_HFROSC_PLL (0)
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#if USE_CLOCK_HFROSC_PLL && (USE_CLOCK_HFXOSC_PLL || USE_CLOCK_HFXOSC)
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#error "Cannot use HFROSC_PLL with HFXOSC based configurations"
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#endif
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#if USE_CLOCK_HFXOSC_PLL && USE_CLOCK_HFXOSC
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#error "Cannot use HFXOSC with HFXOSC_PLL"
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#endif
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#if USE_CLOCK_HFXOSC_PLL
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#define CLOCK_PLL_R (1) /* Divide input clock by 2, mandatory with HFXOSC */
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#define CLOCK_PLL_F (39) /* Multiply REFR by 80, e.g 2 * (39 + 1) */
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#define CLOCK_PLL_Q (1) /* Divide VCO by 2, e.g 2^1 */
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#define CLOCK_PLL_INPUT_CLOCK (16000000UL)
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#define CLOCK_PLL_REFR (CLOCK_PLL_INPUT_CLOCK / (CLOCK_PLL_R + 1))
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#define CLOCK_PLL_VCO (CLOCK_PLL_REFR * (2 * (CLOCK_PLL_F + 1)))
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#define CLOCK_PLL_OUT (CLOCK_PLL_VCO / (1 << CLOCK_PLL_Q))
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#define CLOCK_CORECLOCK (CLOCK_PLL_OUT) /* 320000000Hz with the values used above */
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/* Check PLL settings */
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#if CLOCK_PLL_REFR != 8000000
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#error "Only R=2 can be used when using HFXOSC"
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#endif
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#if (CLOCK_PLL_VCO < 384000000) || (CLOCK_PLL_VCO > 768000000)
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#error "VCO frequency must be in the range [384MHz - 768MHz], check the CLOCK_PLL_F value"
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#endif
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#if (CLOCK_PLL_OUT < 48000000) || (CLOCK_PLL_OUT > 384000000)
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#error "PLL output frequency must be in the range [48MHz - 384MHz], check the CLOCK_PLL_Q value"
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#endif
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#elif USE_CLOCK_HFXOSC
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#define CLOCK_CORECLOCK (16000000UL)
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/*
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When using HFROSC input clock, the core clock cannot be computed from settings,
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call cpu_freq() to get the configured CPU frequency.
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*/
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#elif USE_CLOCK_HFROSC_PLL
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#define CLOCK_DESIRED_FREQUENCY (320000000UL)
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#else
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#define CLOCK_HFROSC_TRIM (6) /* ~72000000Hz input freq */
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#define CLOCK_HFROSC_DIV (1) /* Divide by 2 */
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#endif
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/** @} */
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/**
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* @name Timer configuration
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*
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* @{
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*/
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#define TIMER_NUMOF (1)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.addr = UART0_CTRL_ADDR,
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.rx = GPIO_PIN(0, 16),
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.tx = GPIO_PIN(0, 17),
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.isr_num = INT_UART0_BASE,
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},
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{
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.addr = UART1_CTRL_ADDR,
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.rx = GPIO_PIN(0, 18),
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.tx = GPIO_PIN(0, 23),
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.isr_num = INT_UART1_BASE,
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},
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};
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name RTT/RTC configuration
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*
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* @{
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*/
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#define RTT_FREQUENCY (1) /* in Hz */
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#define RTT_MAX_VALUE (0xFFFFFFFF)
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#define RTT_INTR_PRIORITY (2)
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/** @} */
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/**
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* @name GPIO configuration
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*
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* @{
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*/
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#define GPIO_INTR_PRIORITY (3)
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/** @} */
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/**
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* @name PWM configuration
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*
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* @{
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*/
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#define PWM_NUMOF (3)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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