mirror of
https://github.com/RIOT-OS/RIOT.git
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306 lines
8.0 KiB
C
306 lines
8.0 KiB
C
/*
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* Copyright (C) 2015-2016 Freie Universität Berlin
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* 2017 HAW Hamburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc2538
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Sebastian Meiling <s@mlng.net>
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*/
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#ifndef PERIPH_CPU_H
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#define PERIPH_CPU_H
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#include <stdint.h>
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#include <stdio.h>
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#include "cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Starting offset of CPU_ID
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*/
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#define CPUID_ADDR (&IEEE_ADDR_MSWORD)
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/**
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* @brief Length of the CPU_ID in octets
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*/
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#define CPUID_LEN (8U)
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/**
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* @brief Define a custom type for GPIO pins
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* @{
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*/
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#define HAVE_GPIO_T
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typedef uint32_t gpio_t;
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/** @} */
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/**
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* @name Internal GPIO shift and masking
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* @{
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*/
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#define PORTNUM_MASK (0x00007000) /**< bit mask for GPIO port [0-3] */
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#define PORTNUM_SHIFT (12U) /**< bit shift for GPIO port */
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#define PIN_MASK (0x00000007) /**< bit mask for GPIO pin [0-7] */
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#define GPIO_MASK (0xfffff000) /**< bit mask for GPIO port addr */
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/** @} */
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/**
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* @brief Define a custom GPIO_PIN macro
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*
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* For the CC2538, we use OR the gpio ports base register address with the
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* actual pin number.
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*/
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#define GPIO_PIN(port, pin) (gpio_t)(((uint32_t)GPIO_A + \
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(port << PORTNUM_SHIFT)) | pin)
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/**
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* @brief Access GPIO low-level device
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*
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* @param[in] pin gpio pin
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*
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* @return pointer to gpio low level device address
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*/
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static inline cc2538_gpio_t *gpio(gpio_t pin)
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{
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return (cc2538_gpio_t *)(pin & GPIO_MASK);
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}
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/**
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* @brief Helper function to get port number for gpio pin
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*
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* @param[in] pin gpio pin
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*
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* @return port number of gpio pin, [0=A - 3=D]
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*/
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static inline uint8_t gpio_port_num(gpio_t pin)
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{
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return (uint8_t)((pin & PORTNUM_MASK) >> PORTNUM_SHIFT) - 1;
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}
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/**
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* @brief Helper function to get pin number for gpio pin
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*
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* @param[in] pin gpio pin
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*
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* @return pin number of gpio pin, [0 - 7]
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*/
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static inline uint8_t gpio_pin_num(gpio_t pin)
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{
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return (uint8_t)(pin & PIN_MASK);
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}
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/**
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* @brief Helper function to get bit mask for gpio pin number
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*
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* @param[in] pin gpio pin
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*
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* @return bit mask for gpio pin number, 2^[0 - 7]
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*/
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static inline uint32_t gpio_pin_mask(gpio_t pin)
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{
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return (1 << (pin & PIN_MASK));
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}
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/**
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* @brief Helper function to get CC2538 gpio number from port and pin
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*
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* @param[in] pin gpio pin
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*
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* @return number of gpio pin, [0 - 31]
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*/
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static inline uint8_t gpio_pp_num(gpio_t pin)
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{
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return (uint8_t)((gpio_port_num(pin) * 8) + gpio_pin_num(pin));
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}
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/**
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* @brief Configure an alternate function for the given pin
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*
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* @param[in] pin gpio pin
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* @param[in] sel Setting for IOC select register, (-1) to ignore
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* @param[in] over Setting for IOC override register, (-1) to ignore
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*/
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void gpio_init_af(gpio_t pin, int sel, int over);
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/**
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* @brief Define a custom GPIO_UNDEF value
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*/
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#define GPIO_UNDEF 99
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/**
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* @brief I2C configuration options
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*/
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typedef struct {
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gpio_t scl_pin; /**< pin used for SCL */
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gpio_t sda_pin; /**< pin used for SDA */
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} i2c_conf_t;
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/**
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* @name declare needed generic SPI functions
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* @{
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*/
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#define PERIPH_SPI_NEEDS_INIT_CS
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#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
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#define PERIPH_SPI_NEEDS_TRANSFER_REG
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#define PERIPH_SPI_NEEDS_TRANSFER_REGS
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/** @} */
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/**
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* @name Override the default GPIO mode settings
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* @{
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*/
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#define HAVE_GPIO_MODE_T
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typedef enum {
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GPIO_IN = ((uint8_t)0x00), /**< input, no pull */
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GPIO_IN_PD = ((uint8_t)IOC_OVERRIDE_PDE), /**< input, pull-down */
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GPIO_IN_PU = ((uint8_t)IOC_OVERRIDE_PUE), /**< input, pull-up */
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GPIO_OUT = ((uint8_t)IOC_OVERRIDE_OE), /**< output */
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GPIO_OD = (0xff), /**< not supported */
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GPIO_OD_PU = (0xff) /**< not supported */
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} gpio_mode_t;
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/** @} */
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/**
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* @name Override SPI mode settings
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* @{
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*/
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#define HAVE_SPI_MODE_T
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typedef enum {
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SPI_MODE_0 = 0, /**< CPOL=0, CPHA=0 */
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SPI_MODE_1 = (SSI_CR0_SPH), /**< CPOL=0, CPHA=1 */
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SPI_MODE_2 = (SSI_CR0_SPO), /**< CPOL=1, CPHA=0 */
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SPI_MODE_3 = (SSI_CR0_SPO | SSI_CR0_SPH) /**< CPOL=1, CPHA=1 */
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} spi_mode_t;
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/** @ */
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/**
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* @name Override SPI clock settings
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* @{
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*/
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#define HAVE_SPI_CLK_T
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typedef enum {
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SPI_CLK_100KHZ = 0, /**< drive the SPI bus with 100KHz */
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SPI_CLK_400KHZ = 1, /**< drive the SPI bus with 400KHz */
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SPI_CLK_1MHZ = 2, /**< drive the SPI bus with 1MHz */
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SPI_CLK_5MHZ = 3, /**< drive the SPI bus with 5MHz */
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SPI_CLK_10MHZ = 4 /**< drive the SPI bus with 10MHz */
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} spi_clk_t;
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/** @} */
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/**
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* @brief Datafields for static SPI clock configuration values
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*/
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typedef struct {
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uint8_t cpsr; /**< CPSR clock divider */
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uint8_t scr; /**< SCR clock divider */
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} spi_clk_conf_t;
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/**
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* @name SPI configuration data structure
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* @{
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*/
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typedef struct {
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cc2538_ssi_t *dev; /**< SSI device */
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gpio_t mosi_pin; /**< pin used for MOSI */
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gpio_t miso_pin; /**< pin used for MISO */
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gpio_t sck_pin; /**< pin used for SCK */
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gpio_t cs_pin; /**< pin used for CS */
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} spi_conf_t;
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/** @} */
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/**
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* @brief Timer configuration data
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*/
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typedef struct {
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cc2538_gptimer_t *dev; /**< timer device */
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uint_fast8_t channels; /**< number of channels */
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uint_fast8_t cfg; /**< timer config word */
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} timer_conf_t;
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/**
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* @name Override resolution options
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* @{
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*/
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#define HAVE_ADC_RES_T
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typedef enum {
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ADC_RES_6BIT = (0xa00), /**< not supported by hardware */
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ADC_RES_7BIT = (0 << 4), /**< ADC resolution: 7 bit */
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ADC_RES_8BIT = (0xb00), /**< not supported by hardware */
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ADC_RES_9BIT = (1 << 4), /**< ADC resolution: 9 bit */
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ADC_RES_10BIT = (2 << 4), /**< ADC resolution: 10 bit */
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ADC_RES_12BIT = (3 << 4), /**< ADC resolution: 12 bit */
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ADC_RES_14BIT = (0xc00), /**< not supported by hardware */
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ADC_RES_16BIT = (0xd00), /**< not supported by hardware */
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} adc_res_t;
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/** @} */
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/**
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* @brief ADC configuration wrapper
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*/
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typedef gpio_t adc_conf_t;
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/**
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* @name SOC_ADC_ADCCON3 register bit masks
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* @{
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*/
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#define SOC_ADC_ADCCON3_EREF (0x000000C0) /**< Reference voltage for extra */
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#define SOC_ADC_ADCCON3_EDIV (0x00000030) /**< Decimation rate for extra */
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#define SOC_ADC_ADCCON3_ECH (0x0000000F) /**< Single channel select */
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/** @} */
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/**
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* @name SOC_ADC_ADCCONx registers field values
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* @{
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*/
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#define SOC_ADC_ADCCON_REF_INT (0 << 6) /**< Internal reference */
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#define SOC_ADC_ADCCON_REF_EXT (1 << 6) /**< External reference on AIN7 pin */
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#define SOC_ADC_ADCCON_REF_AVDD5 (2 << 6) /**< AVDD5 pin */
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#define SOC_ADC_ADCCON_REF_DIFF (3 << 6) /**< External reference on AIN6-AIN7 differential input */
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#define SOC_ADC_ADCCON_CH_GND (0xC) /**< GND */
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/** @} */
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/**
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* @brief Mask to check end-of-conversion (EOC) bit
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*/
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#define SOC_ADC_ADCCON1_EOC_MASK (0x80)
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/**
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* @name Masks for ADC raw data
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* @{
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*/
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#define SOC_ADC_ADCL_MASK (0x000000FC)
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#define SOC_ADC_ADCH_MASK (0x000000FF)
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/** @} */
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/**
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* @name Bit shift for data per ADC resolution
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* @{
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*/
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#define SOCADC_7_BIT_RSHIFT (9U) /**< Mask for getting data( 7 bits ENOB) */
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#define SOCADC_9_BIT_RSHIFT (7U) /**< Mask for getting data( 9 bits ENOB) */
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#define SOCADC_10_BIT_RSHIFT (6U) /**< Mask for getting data(10 bits ENOB) */
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#define SOCADC_12_BIT_RSHIFT (4U) /**< Mask for getting data(12 bits ENOB) */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#include "periph/dev_enums.h"
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#endif /* PERIPH_CPU_H */
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/** @} */
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