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467 lines
15 KiB
C
467 lines
15 KiB
C
/******************************************************************************
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* Filename: cpu.h
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* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018)
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* Revision: 52111
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*
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* Description: Defines and prototypes for the CPU instruction wrapper
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* functions.
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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//*****************************************************************************
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//
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//! \addtogroup system_cpu_group
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//! @{
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//! \addtogroup cpu_api
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//! @{
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//
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//*****************************************************************************
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#ifndef __CPU_H__
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#define __CPU_H__
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//*****************************************************************************
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//
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// If building with a C++ compiler, make all of the definitions in this header
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// have a C binding.
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//
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//*****************************************************************************
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include <stdbool.h>
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#include <stdint.h>
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#include "../inc/hw_types.h"
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#include "../inc/hw_memmap.h"
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#include "../inc/hw_cpu_scs.h"
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//*****************************************************************************
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//
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// Support for DriverLib in ROM:
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// This section renames all functions that are not "static inline", so that
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// calling these functions will default to implementation in flash. At the end
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// of this file a second renaming will change the defaults to implementation in
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// ROM for available functions.
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//
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// To force use of the implementation in flash, e.g. for debugging:
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// - Globally: Define DRIVERLIB_NOROM at project level
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// - Per function: Use prefix "NOROM_" when calling the function
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//
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//*****************************************************************************
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#if !defined(DOXYGEN)
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#define CPUcpsid NOROM_CPUcpsid
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#define CPUprimask NOROM_CPUprimask
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#define CPUcpsie NOROM_CPUcpsie
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#define CPUbasepriGet NOROM_CPUbasepriGet
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#define CPUdelay NOROM_CPUdelay
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#endif
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//*****************************************************************************
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//
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// API Functions and prototypes
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \brief Disable all external interrupts.
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//!
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//! Use this function to disable all system interrupts. This function is
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//! implemented as a wrapper function for the CPSID instruction.
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//!
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//! \return Returns the state of \b PRIMASK on entry
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//
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//*****************************************************************************
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extern uint32_t CPUcpsid(void);
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//*****************************************************************************
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//
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//! \brief Get the current interrupt state.
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//!
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//! Use this function to retrieve the current state of the interrupts. This
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//! function is implemented as a wrapper function returning the state of
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//! PRIMASK.
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//!
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//! \return Returns the state of the \b PRIMASK (indicating whether interrupts
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//! are enabled or disabled).
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//
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//*****************************************************************************
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extern uint32_t CPUprimask(void);
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//*****************************************************************************
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//
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//! \brief Enable all external interrupts.
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//!
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//! Use this function to enable all system interrupts. This function is
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//! implemented as a wrapper function for the CPSIE instruction.
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//!
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//! \return Returns the state of \b PRIMASK on entry.
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//
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//*****************************************************************************
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extern uint32_t CPUcpsie(void);
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//*****************************************************************************
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//
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//! \brief Get the interrupt priority disable level.
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//!
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//! Use this function to get the level of priority that will disable
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//! interrupts with a lower priority level.
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//!
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//! \return Returns the value of the \b BASEPRI register.
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//
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//*****************************************************************************
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extern uint32_t CPUbasepriGet(void);
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//*****************************************************************************
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//
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//! \brief Provide a small non-zero delay using a simple loop counter.
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//!
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//! This function provides means for generating a constant length delay. It
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//! is written in assembly to keep the delay consistent across tool chains,
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//! avoiding the need to tune the delay based on the tool chain in use.
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//!
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//! \note It is not recommended using this function for long delays.
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//!
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//! Notice that interrupts can affect the delay if not manually disabled in advance.
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//!
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//! The delay depends on where code resides and the path for code fetching:
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//! - Code in flash, cache enabled, prefetch enabled : 4 cycles per loop (Default)
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//! - Code in flash, cache enabled, prefetch disabled : 5 cycles per loop
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//! - Code in flash, cache disabled : 7 cycles per loop
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//! - Code in SRAM : 6 cycles per loop
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//! - Code in GPRAM : 3 cycles per loop
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//!
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//! \note If using an RTOS, consider using RTOS provided delay functions because
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//! these will not block task scheduling and will potentially save power.
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//!
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//! Calculate delay count based on the wanted delay in microseconds (us):
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//! - ui32Count = [delay in us] * [CPU clock in MHz] / [cycles per loop]
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//!
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//! Example: 250 us delay with code in flash and with cache and prefetch enabled:
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//! - ui32Count = 250 * 48 / 4 = 3000
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//!
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//! \param ui32Count is the number of delay loop iterations to perform. Number must be greater than zero.
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//!
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//! \return None
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//
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//*****************************************************************************
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extern void CPUdelay(uint32_t ui32Count);
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//*****************************************************************************
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//
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//! \brief Wait for interrupt.
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//!
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//! Use this function to let the System CPU wait for the next interrupt. This
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//! function is implemented as a wrapper function for the WFI instruction.
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//!
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//! \return None
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//
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//*****************************************************************************
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#if defined(DOXYGEN)
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__STATIC_INLINE void
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CPUwfi(void)
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{
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// This function is written in assembly. See cpu.h for compiler specific implementation.
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}
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#elif defined(__IAR_SYSTEMS_ICC__)
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__STATIC_INLINE void
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CPUwfi(void)
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{
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// Wait for the next interrupt.
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__asm(" wfi\n");
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}
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#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
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__asm __STATIC_INLINE void
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CPUwfi(void)
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{
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// Wait for the next interrupt.
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wfi;
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bx lr
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}
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#elif defined(__TI_COMPILER_VERSION__)
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__STATIC_INLINE void
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CPUwfi(void)
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{
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// Wait for the next interrupt.
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__asm(" wfi\n");
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}
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#else
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__STATIC_INLINE void __attribute__((always_inline))
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CPUwfi(void)
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{
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// Wait for the next interrupt.
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__asm volatile (" wfi\n");
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}
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#endif
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//*****************************************************************************
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//
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//! \brief Wait for event.
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//!
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//! Use this function to let the System CPU wait for the next event. This
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//! function is implemented as a wrapper function for the WFE instruction.
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//!
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//! \return None
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//
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//*****************************************************************************
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#if defined(DOXYGEN)
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__STATIC_INLINE void
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CPUwfe(void)
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{
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// This function is written in assembly. See cpu.h for compiler specific implementation.
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}
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#elif defined(__IAR_SYSTEMS_ICC__)
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__STATIC_INLINE void
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CPUwfe(void)
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{
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// Wait for the next event.
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__asm(" wfe\n");
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}
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#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
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__asm __STATIC_INLINE void
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CPUwfe(void)
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{
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// Wait for the next event.
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wfe;
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bx lr
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}
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#elif defined(__TI_COMPILER_VERSION__)
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__STATIC_INLINE void
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CPUwfe(void)
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{
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// Wait for the next event.
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__asm(" wfe\n");
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}
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#else
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__STATIC_INLINE void __attribute__((always_inline))
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CPUwfe(void)
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{
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// Wait for the next event.
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__asm volatile (" wfe\n");
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}
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#endif
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//*****************************************************************************
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//
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//! \brief Send event.
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//!
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//! Use this function to let the System CPU send an event. This function is
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//! implemented as a wrapper function for the SEV instruction.
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//!
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//! \return None
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//
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//*****************************************************************************
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#if defined(DOXYGEN)
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__STATIC_INLINE void
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CPUsev(void)
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{
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// This function is written in assembly. See cpu.h for compiler specific implementation.
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}
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#elif defined(__IAR_SYSTEMS_ICC__)
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__STATIC_INLINE void
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CPUsev(void)
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{
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// Send event.
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__asm(" sev\n");
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}
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#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
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__asm __STATIC_INLINE void
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CPUsev(void)
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{
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// Send event.
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sev;
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bx lr
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}
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#elif defined(__TI_COMPILER_VERSION__)
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__STATIC_INLINE void
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CPUsev(void)
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{
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// Send event.
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__asm(" sev\n");
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}
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#else
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__STATIC_INLINE void __attribute__((always_inline))
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CPUsev(void)
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{
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// Send event.
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__asm volatile (" sev\n");
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}
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#endif
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//*****************************************************************************
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//
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//! \brief Update the interrupt priority disable level.
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//!
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//! Use this function to change the level of priority that will disable
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//! interrupts with a lower priority level.
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//!
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//! \param ui32NewBasepri is the new basis priority level to set.
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//!
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//! \return None
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//
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//*****************************************************************************
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#if defined(DOXYGEN)
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__STATIC_INLINE void
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CPUbasepriSet(uint32_t ui32NewBasepri)
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{
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// This function is written in assembly. See cpu.h for compiler specific implementation.
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}
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#elif defined(__IAR_SYSTEMS_ICC__)
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__STATIC_INLINE void
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CPUbasepriSet(uint32_t ui32NewBasepri)
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{
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// Set the BASEPRI register.
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__asm(" msr BASEPRI, r0\n");
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}
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#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
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__asm __STATIC_INLINE void
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CPUbasepriSet(uint32_t ui32NewBasepri)
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{
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// Set the BASEPRI register.
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msr BASEPRI, r0;
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bx lr
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}
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#elif defined(__TI_COMPILER_VERSION__)
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__STATIC_INLINE void
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CPUbasepriSet(uint32_t ui32NewBasepri)
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{
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// Set the BASEPRI register.
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__asm(" msr BASEPRI, r0\n");
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}
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#else
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wattributes"
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__STATIC_INLINE void __attribute__ ((naked))
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CPUbasepriSet(uint32_t ui32NewBasepri)
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{
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// Set the BASEPRI register.
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__asm volatile (" msr BASEPRI, %0\n"
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" bx lr\n"
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: /* No output */
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: "r" (ui32NewBasepri)
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);
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}
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#pragma GCC diagnostic pop
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#endif
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//*****************************************************************************
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//
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//! \brief Disable CPU write buffering (recommended for debug purpose only).
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//!
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//! This function helps debugging "bus fault crashes".
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//! Disables write buffer use during default memory map accesses.
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//!
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//! This causes all bus faults to be precise bus faults but decreases the
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//! performance of the processor because the stores to memory have to complete
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//! before the next instruction can be executed.
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//!
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//! \return None
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//!
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//! \sa \ref CPU_WriteBufferEnable()
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//
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//*****************************************************************************
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__STATIC_INLINE void
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CPU_WriteBufferDisable( void )
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{
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HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 1;
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}
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//*****************************************************************************
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//
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//! \brief Enable CPU write buffering (default setting).
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//!
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//! Re-enables write buffer during default memory map accesses if
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//! \ref CPU_WriteBufferDisable() has been used for bus fault debugging.
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//!
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//! \return None
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//!
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//! \sa \ref CPU_WriteBufferDisable()
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//
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//*****************************************************************************
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__STATIC_INLINE void
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CPU_WriteBufferEnable( void )
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{
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HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 0;
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}
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//*****************************************************************************
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//
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// Support for DriverLib in ROM:
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// Redirect to implementation in ROM when available.
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//
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//*****************************************************************************
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#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
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#include "../driverlib/rom.h"
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#ifdef ROM_CPUcpsid
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#undef CPUcpsid
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#define CPUcpsid ROM_CPUcpsid
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#endif
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#ifdef ROM_CPUprimask
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#undef CPUprimask
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#define CPUprimask ROM_CPUprimask
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#endif
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#ifdef ROM_CPUcpsie
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#undef CPUcpsie
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#define CPUcpsie ROM_CPUcpsie
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#endif
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#ifdef ROM_CPUbasepriGet
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#undef CPUbasepriGet
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#define CPUbasepriGet ROM_CPUbasepriGet
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#endif
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#ifdef ROM_CPUdelay
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#undef CPUdelay
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#define CPUdelay ROM_CPUdelay
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#endif
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#endif
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//*****************************************************************************
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//
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// Mark the end of the C bindings section for C++ compilers.
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//
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//*****************************************************************************
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#ifdef __cplusplus
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}
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#endif
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#endif // __CPU_H__
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//*****************************************************************************
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//
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//! Close the Doxygen group.
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//! @}
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//! @}
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//
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//*****************************************************************************
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