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68 lines
1.4 KiB
C
68 lines
1.4 KiB
C
/*
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* Copyright (C) 2019 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @defgroup cpu_stm32wb STM32WB
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* @brief STM32WB specific code
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* @ingroup cpu
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* @{
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*
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* @file
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* @brief Implementation specific CPU configuration options
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*
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* @author Francisco Molina <francois-xavier.molina@inria.fr>
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*
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*/
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#ifndef CPU_CONF_H
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#define CPU_CONF_H
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#include "cpu_conf_common.h"
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#if defined(CPU_MODEL_STM32WB55RG)
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#include "vendor/stm32wb55xx.h"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief ARM Cortex-M specific CPU configuration
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* @{
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*/
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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#if defined(CPU_MODEL_STM32WB55RG)
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#define CPU_IRQ_NUMOF (63U)
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#endif
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#define CPU_FLASH_BASE FLASH_BASE
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/** @} */
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/**
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* @name Flash page configuration
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* @{
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*/
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#define FLASHPAGE_SIZE (4096U)
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#define FLASHPAGE_NUMOF (STM32_FLASHSIZE / FLASHPAGE_SIZE)
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/* The minimum block size which can be written is 8B. However, the erase
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* block is always FLASHPAGE_SIZE.
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*/
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#define FLASHPAGE_RAW_BLOCKSIZE (8U)
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/* Writing should be always 8 bytes aligned */
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#define FLASHPAGE_RAW_ALIGNMENT (8U)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPU_CONF_H */
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/** @} */
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