mirror of
https://github.com/RIOT-OS/RIOT.git
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45edfa43bf
These pins have no alternate function in the pin mux so we might as well make them available to applications. These pins are the only pins which provide differential analog input pairs on this board.
275 lines
8.9 KiB
C
275 lines
8.9 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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* Copyright (C) 2015 PHYTEC Messtechnik GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_frdm-k64f
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* @{
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*
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* @file
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* @name Peripheral MCU configuration for the FRDM-K64F
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*
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* @author Johann Fischer <j.fischer@phytec.de>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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static const clock_config_t clock_config = {
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/*
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* This configuration results in the system running from the PLL output with
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* the following clock frequencies:
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* Core: 60 MHz
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* Bus: 60 MHz
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* Flex: 20 MHz
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* Flash: 20 MHz
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*/
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.clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
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SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(2),
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.rtc_clc = 0, /* External load caps on board */
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.osc32ksel = SIM_SOPT1_OSC32KSEL(2),
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.clock_flags =
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/* No OSC0_EN, use EXTAL directly without OSC0 */
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KINETIS_CLOCK_RTCOSC_EN |
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KINETIS_CLOCK_USE_FAST_IRC |
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0,
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.default_mode = KINETIS_MCG_MODE_PEE,
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/* The board has an external RMII (Ethernet) clock which drives the ERC at 50 MHz */
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.erc_range = KINETIS_MCG_ERC_RANGE_VERY_HIGH,
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.osc_clc = 0, /* External load caps on board */
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.oscsel = MCG_C7_OSCSEL(0), /* Use EXTAL for external clock */
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.fcrdiv = MCG_SC_FCRDIV(0), /* Fast IRC divide by 1 => 4 MHz */
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.fll_frdiv = MCG_C1_FRDIV(0b111), /* Divide by 1536 => FLL input 32252 Hz */
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.fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
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.fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1920, /* FLL freq = 62.5 MHz */
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.pll_prdiv = MCG_C5_PRDIV0(0b10011), /* Divide by 20 */
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.pll_vdiv = MCG_C6_VDIV0(0b00000), /* Multiply by 24 => PLL freq = 60 MHz */
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};
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#define CLOCK_CORECLOCK (60000000ul)
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#define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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#define PIT_NUMOF (2U)
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#define PIT_CONFIG { \
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{ \
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.prescaler_ch = 0, \
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.count_ch = 1, \
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}, \
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{ \
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.prescaler_ch = 2, \
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.count_ch = 3, \
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}, \
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}
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#define LPTMR_NUMOF (0U)
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#define LPTMR_CONFIG {}
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#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
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#define PIT_BASECLOCK (CLOCK_BUSCLOCK)
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#define PIT_ISR_0 isr_pit1
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#define PIT_ISR_1 isr_pit3
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#define LPTMR_ISR_0 isr_lptmr0
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = UART0,
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.freq = CLOCK_CORECLOCK,
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.pin_rx = GPIO_PIN(PORT_B, 16),
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.pin_tx = GPIO_PIN(PORT_B, 17),
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.pcr_rx = PORT_PCR_MUX(3),
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.pcr_tx = PORT_PCR_MUX(3),
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.irqn = UART0_RX_TX_IRQn,
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.scgc_addr = &SIM->SCGC4,
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.scgc_bit = SIM_SCGC4_UART0_SHIFT,
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.mode = UART_MODE_8N1,
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.type = KINETIS_UART,
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},
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};
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#define UART_0_ISR (isr_uart0_rx_tx)
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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static const adc_conf_t adc_config[] = {
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[ 0] = { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 2), .chan = 12 }, /* PTB2 (Arduino A0) */
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[ 1] = { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 3), .chan = 13 }, /* PTB3 (Arduino A1) */
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[ 2] = { .dev = ADC1, .pin = GPIO_PIN(PORT_B, 10), .chan = 14 }, /* PTB10 (Arduino A2) */
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[ 3] = { .dev = ADC1, .pin = GPIO_PIN(PORT_B, 11), .chan = 15 }, /* PTB11 (Arduino A3) */
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[ 4] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 11), .chan = 7 }, /* PTC11 (Arduino A4) */
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[ 5] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 10), .chan = 6 }, /* PTC10 (Arduino A5) */
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[ 6] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 0 }, /* ADC0_DP0 */
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[ 7] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 19 }, /* ADC0_DM0 */
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[ 8] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = (0 | ADC_SC1_DIFF_MASK) }, /* ADC0_DP0 - ADC0_DM0 */
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[ 9] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 0 }, /* ADC1_DP0 */
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[10] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 19 }, /* ADC1_DM0 */
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[11] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = (0 | ADC_SC1_DIFF_MASK) }, /* ADC1_DP0 - ADC1_DM0 */
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[12] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 1 }, /* ADC0_DP1 */
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[13] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 20 }, /* ADC0_DM1 */
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[14] = { .dev = ADC0, .pin = GPIO_UNDEF , .chan = (1 | ADC_SC1_DIFF_MASK) }, /* ADC0_DP1 - ADC0_DM1 */
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[15] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 1 }, /* ADC1_DP1 */
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[16] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 20 }, /* ADC1_DM1 */
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[17] = { .dev = ADC1, .pin = GPIO_UNDEF , .chan = (1 | ADC_SC1_DIFF_MASK) }, /* ADC1_DP1 - ADC1_DM1 */
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/* internal: temperature sensor */
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/* The temperature sensor has a very high output impedance, it must not be
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* sampled using hardware averaging, or the sampled values will be garbage */
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[18] = { .dev = ADC0, .pin = GPIO_UNDEF, .chan = 26 },
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/* internal: band gap */
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/* Note: the band gap buffer uses a bit of current and is turned off by default,
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* Set PMC->REGSC |= PMC_REGSC_BGBE_MASK before reading or the input will be floating */
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[19] = { .dev = ADC0, .pin = GPIO_UNDEF, .chan = 27 },
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};
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#define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
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/*
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* K64F ADC reference settings:
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* 0: VREFH/VREFL external pin pair
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* 1: VREF_OUT internal 1.2 V reference (VREF module must be enabled)
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* 2-3: reserved
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*/
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#define ADC_REF_SETTING 0
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.ftm = FTM0,
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.chan = {
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{ .pin = GPIO_PIN(PORT_A, 4), .af = 3, .ftm_chan = 6 },
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{ .pin = GPIO_PIN(PORT_A, 2), .af = 3, .ftm_chan = 7 },
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{ .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
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{ .pin = GPIO_PIN(PORT_C, 3), .af = 4, .ftm_chan = 2 }
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},
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.chan_numof = 4,
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.ftm_num = 0
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}
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};
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#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
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/** @} */
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/**
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* @name SPI configuration
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*
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* Clock configuration values based on the configured 30Mhz module clock.
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*
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* Auto-generated by:
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* cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
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*
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* @{
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*/
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static const uint32_t spi_clk_config[] = {
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(
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SPI_CTAR_PBR(2) | SPI_CTAR_BR(6) | /* -> 93750Hz */
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SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(5) |
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SPI_CTAR_PASC(2) | SPI_CTAR_ASC(5) |
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SPI_CTAR_PDT(2) | SPI_CTAR_DT(5)
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),
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(
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SPI_CTAR_PBR(2) | SPI_CTAR_BR(4) | /* -> 375000Hz */
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SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(3) |
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SPI_CTAR_PASC(2) | SPI_CTAR_ASC(3) |
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SPI_CTAR_PDT(2) | SPI_CTAR_DT(3)
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),
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(
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SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) | /* -> 1000000Hz */
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SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(4) |
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SPI_CTAR_PASC(0) | SPI_CTAR_ASC(4) |
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SPI_CTAR_PDT(0) | SPI_CTAR_DT(4)
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),
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(
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SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 5000000Hz */
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SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
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SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
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SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
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),
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(
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SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 7500000Hz */
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SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
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SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
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SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
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)
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI0,
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.pin_miso = GPIO_PIN(PORT_D, 3),
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.pin_mosi = GPIO_PIN(PORT_D, 2),
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.pin_clk = GPIO_PIN(PORT_D, 1),
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.pin_cs = {
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GPIO_PIN(PORT_D, 0),
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GPIO_UNDEF,
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GPIO_UNDEF,
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GPIO_UNDEF,
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GPIO_UNDEF
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},
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.pcr = GPIO_AF_2,
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.simmask = SIM_SCGC6_SPI0_MASK
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}
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};
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#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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static const i2c_conf_t i2c_config[] = {
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{
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.i2c = I2C0,
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.scl_pin = GPIO_PIN(PORT_E, 24),
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.sda_pin = GPIO_PIN(PORT_E, 25),
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.freq = CLOCK_BUSCLOCK,
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.speed = I2C_SPEED_FAST,
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.irqn = I2C0_IRQn,
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.scl_pcr = (PORT_PCR_MUX(5) | PORT_PCR_ODE_MASK),
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.sda_pcr = (PORT_PCR_MUX(5) | PORT_PCR_ODE_MASK),
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},
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};
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#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
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#define I2C_0_ISR (isr_i2c0)
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#define I2C_1_ISR (isr_i2c1)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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