mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2025-01-18 12:52:44 +01:00
459f7ebce0
The SPI bus frequency/clock is calculated relative to the MCUs core clock. Currently all boards use the default 32MHz, hence prescaler settings for SPI are all the same. This PR moves the default config for 32MHz to the CPU and allows to be overriden by board config if needed.
143 lines
2.8 KiB
C
143 lines
2.8 KiB
C
/*
|
|
* Copyright (C) 2014 Loci Controls Inc.
|
|
*
|
|
* This file is subject to the terms and conditions of the GNU Lesser
|
|
* General Public License v2.1. See the file LICENSE in the top level
|
|
* directory for more details.
|
|
*/
|
|
|
|
/**
|
|
* @ingroup boards_cc2538dk
|
|
* @{
|
|
*
|
|
* @file
|
|
* @brief Peripheral MCU configuration for the CC2538DK board
|
|
*
|
|
* @author Ian Martin <ian@locicontrols.com>
|
|
*/
|
|
|
|
#ifndef PERIPH_CONF_H
|
|
#define PERIPH_CONF_H
|
|
|
|
#include "cpu.h"
|
|
#include "periph_cpu.h"
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
/**
|
|
* @name Timer configuration
|
|
*
|
|
* General purpose timers (GPT[0-3]) are configured consecutively and in order
|
|
* (without gaps) starting from GPT0, i.e. if multiple timers are enabled.
|
|
*
|
|
* @{
|
|
*/
|
|
static const timer_conf_t timer_config[] = {
|
|
{
|
|
.chn = 2,
|
|
.cfg = GPTMCFG_16_BIT_TIMER, /* required for XTIMER */
|
|
},
|
|
{
|
|
.chn = 1,
|
|
.cfg = GPTMCFG_32_BIT_TIMER,
|
|
},
|
|
{
|
|
.chn = 2,
|
|
.cfg = GPTMCFG_16_BIT_TIMER,
|
|
},
|
|
{
|
|
.chn = 1,
|
|
.cfg = GPTMCFG_32_BIT_TIMER,
|
|
},
|
|
};
|
|
|
|
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
|
|
|
|
#define TIMER_IRQ_PRIO 1
|
|
/** @} */
|
|
|
|
/**
|
|
* @name UART configuration
|
|
* @{
|
|
*/
|
|
static const uart_conf_t uart_config[] = {
|
|
{
|
|
.dev = UART0_BASEADDR,
|
|
.rx_pin = GPIO_PIN(0, 0),
|
|
.tx_pin = GPIO_PIN(0, 1),
|
|
.cts_pin = GPIO_UNDEF,
|
|
.rts_pin = GPIO_UNDEF
|
|
}
|
|
};
|
|
|
|
/* interrupt function name mapping */
|
|
#define UART_0_ISR isr_uart0
|
|
|
|
/* macros common across all UARTs */
|
|
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
|
|
|
|
/** @} */
|
|
|
|
/**
|
|
* @name I2C configuration
|
|
* @{
|
|
*/
|
|
#define I2C_IRQ_PRIO 1
|
|
|
|
static const i2c_conf_t i2c_config[] = {
|
|
{
|
|
.speed = I2C_SPEED_FAST, /**< bus speed */
|
|
.scl_pin = GPIO_PIN(0, 2), /**< GPIO_PA2, SPI_SCK on SmartRF06 */
|
|
.sda_pin = GPIO_PIN(0, 4) /**< GPIO_PA4, SPI_MOSI on SmartRF06 */
|
|
},
|
|
};
|
|
|
|
#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
|
|
/** @} */
|
|
|
|
/**
|
|
* @name SPI configuration
|
|
* @{
|
|
*/
|
|
static const spi_conf_t spi_config[] = {
|
|
{
|
|
.dev = SSI0,
|
|
.mosi_pin = GPIO_PA4,
|
|
.miso_pin = GPIO_PA5,
|
|
.sck_pin = GPIO_PA2,
|
|
.cs_pin = GPIO_PD0
|
|
}
|
|
};
|
|
|
|
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
|
|
/** @} */
|
|
|
|
/**
|
|
* @name ADC configuration
|
|
* @{
|
|
*/
|
|
#define SOC_ADC_ADCCON_REF SOC_ADC_ADCCON_REF_AVDD5
|
|
|
|
static const adc_conf_t adc_config[] = {
|
|
GPIO_PIN(0, 6), /**< GPIO_PA6 = ADC_ALS_PIN */
|
|
};
|
|
|
|
#define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
|
|
/** @} */
|
|
|
|
/**
|
|
* @name Radio peripheral configuration
|
|
* @{
|
|
*/
|
|
#define RADIO_IRQ_PRIO 1
|
|
/** @} */
|
|
|
|
#ifdef __cplusplus
|
|
} /* end extern "C" */
|
|
#endif
|
|
|
|
#endif /* PERIPH_CONF_H */
|
|
/** @} */
|