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117 lines
3.0 KiB
C
117 lines
3.0 KiB
C
/*
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* Copyright (C) 2015 HAW Hamburg
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* 2016 Freie Universität Berlin
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* 2016 INRIA
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_atmega_common
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author René Herthel <rene-herthel@outlook.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Francisco Acosta <francisco.acosta@inria.fr>
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*/
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#ifndef PERIPH_CPU_COMMON_H
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#define PERIPH_CPU_COMMON_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Define a CPU specific GPIO pin generator macro
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*/
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#define GPIO_PIN(x, y) ((x << 4) | y)
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/**
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* @brief Override the GPIO flanks
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*
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* This device has an additional mode in which the interrupt is triggered
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* when the pin is low.
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*
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* Enumeration order is important, do not modify.
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* @{
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*/
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#define HAVE_GPIO_FLANK_T
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typedef enum {
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GPIO_LOW, /**< emit interrupt when pin low */
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GPIO_BOTH, /**< emit interrupt on both flanks */
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GPIO_FALLING, /**< emit interrupt on falling flank */
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GPIO_RISING, /**< emit interrupt on rising flank */
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} gpio_flank_t;
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/** @} */
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/**
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* @brief Use some common SPI functions
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* @{
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*/
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#define PERIPH_SPI_NEEDS_INIT_CS
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#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
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#define PERIPH_SPI_NEEDS_TRANSFER_REG
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#define PERIPH_SPI_NEEDS_TRANSFER_REGS
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/** @} */
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/**
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* @brief SPI mode select macro
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*
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* The polarity is determined by bit 3 in the configuration register, the phase
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* by bit 2.
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*/
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#define SPI_MODE_SEL(pol, pha) ((pol << 3) | (pha << 2))
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/**
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* @brief Override the SPI mode values
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*
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* As the mode is set in bit 3 and 2 of the configuration register, we put the
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* correct configuration there
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* @{
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*/
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#define HAVE_SPI_MODE_T
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typedef enum {
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SPI_MODE_0 = SPI_MODE_SEL(0, 0), /**< mode 0 */
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SPI_MODE_1 = SPI_MODE_SEL(0, 1), /**< mode 1 */
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SPI_MODE_2 = SPI_MODE_SEL(1, 0), /**< mode 2 */
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SPI_MODE_3 = SPI_MODE_SEL(1, 1) /**< mode 3 */
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} spi_mode_t;
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/** @} */
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/**
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* @brief SPI speed selection macro
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*
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* We encode the speed in bits 2, 1, and 0, where bit0 and bit1 hold the SPCR
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* prescaler bits, while bit2 holds the SPI2X bit.
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*/
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#define SPI_CLK_SEL(s2x, pr1, pr0) ((s2x << 2) | (pr1 << 1) | pr0)
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/**
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* @brief Override SPI speed values
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*
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* We assume a master clock speed of 16MHz here.
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* @{
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*/
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#define HAVE_SPI_CLK_T
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typedef enum {
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SPI_CLK_100KHZ = SPI_CLK_SEL(0, 1, 1), /**< 16/128 -> 125KHz */
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SPI_CLK_400KHZ = SPI_CLK_SEL(1, 1, 0), /**< 16/32 -> 500KHz */
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SPI_CLK_1MHZ = SPI_CLK_SEL(0, 0, 1), /**< 16/16 -> 1MHz */
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SPI_CLK_5MHZ = SPI_CLK_SEL(0, 0, 0), /**< 16/4 -> 4MHz */
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SPI_CLK_10MHZ = SPI_CLK_SEL(1, 0, 0) /**< 16/2 -> 8MHz */
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} spi_clk_t;
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_COMMON_H */
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/** @} */
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