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87 lines
2.3 KiB
C
87 lines
2.3 KiB
C
/*
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* Copyright 2020 Koen Zandberg
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* 2023 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_gd32v
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* @{
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*
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* @brief Implementation of the CPU power management for Gigadevice GD32V
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*
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* @author Koen Zandberg <koen@bergzand.net>
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* @author Gunar Schorcht <gunar@schorcht.net>
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* @}
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include "periph/pm.h"
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#include "periph/wdt.h"
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#undef MCAUSE_CAUSE /* redefined in NMSIS header */
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#include "core_feature_base.h"
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void pm_set(unsigned mode)
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{
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bool csr_deepsleep = false; /* RISC-V sleep mode */
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switch (mode) {
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case GD32V_PM_STANDBY:
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csr_deepsleep = true;
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/* set the STANDBY mode flag */
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PMU->CTL |= PMU_CTL_WURST_Msk;
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/* reset the wake up flag */
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PMU->CTL |= PMU_CTL_STBMOD_Msk;
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break;
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case GD32V_PM_DEEPSLEEP:
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csr_deepsleep = true;
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/* reset the STANDBY mode flag */
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PMU->CTL &= ~PMU_CTL_STBMOD_Msk;
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/* use LDO low powered in deep sleep mode */
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PMU->CTL |= PMU_CTL_LDOLP_Msk;
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break;
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case GD32V_PM_IDLE:
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csr_deepsleep = false;
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break;
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default:
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break;
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}
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if (csr_deepsleep) {
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/* Enable WKUP pin if used */
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PMU->CS &= ~PMU_CS_WUPEN_Msk;
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PMU->CS |= (CONFIG_PM_EWUP_USED) ? PMU_CS_WUPEN_Msk : 0;
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/* set CSR_SLEEPVALUE bit in RISC-V system control register */
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__set_wfi_sleepmode(WFI_DEEP_SLEEP);
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}
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else {
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/* clear CSR_SLEEPVALUE bit in RISC-V system control register */
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__set_wfi_sleepmode(WFI_SHALLOW_SLEEP);
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}
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/* trigger sleeping, TODO wait for wake up event (__WFE) implementation */
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__WFI();
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if (csr_deepsleep) {
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/* clear CSR_SLEEPVALUE bit in RISC-V system control register */
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__set_wfi_sleepmode(WFI_SHALLOW_SLEEP);
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/* after deep sleep, the IRC8M is used as clock so that a clock
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* reinitialization is required */
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gd32vf103_clock_init();
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}
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}
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void pm_reboot(void)
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{
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wdt_setup_reboot(0, 1);
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wdt_start();
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wdt_kick();
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while (1) {}
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}
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