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https://github.com/RIOT-OS/RIOT.git
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135 lines
4.3 KiB
C
135 lines
4.3 KiB
C
/*
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* Copyright (C) 2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Implementation of STM32 clock configuration for the G4 family
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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* @}
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*/
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#include "cpu.h"
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#include "stmclk.h"
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#include "periph_conf.h"
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#if CLOCK_USE_HSE && CLOCK_HSE == 0
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#error "HSE is selected as input clock source but CLOCK_HSE is not set"
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#endif
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#if CLOCK_USE_PLL
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#if (CLOCK_PLL_M < 1 || CLOCK_PLL_M > 16)
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#error "PLL configuration: PLL M value is out of range"
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#endif
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#define PLL_M ((CLOCK_PLL_M - 1) << RCC_PLLCFGR_PLLM_Pos)
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#if (CLOCK_PLL_N < 8 || CLOCK_PLL_N > 127)
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#error "PLL configuration: PLL N value is out of range"
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#endif
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#define PLL_N (CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
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#if (CLOCK_PLL_R < 1 || CLOCK_PLL_R > 8)
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#error "PLL configuration: PLL R value is out of range"
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#endif
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#define PLL_R (((CLOCK_PLL_R >> 1) - 1) << RCC_PLLCFGR_PLLR_Pos)
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#if CLOCK_HSE
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#define PLL_IN CLOCK_HSE
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
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#else
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#define PLL_IN CLOCK_HSI
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI
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#endif
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#endif /* CLOCK_USE_PLL */
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/** Determine the required flash wait states from the core clock frequency */
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#if CLOCK_AHB >= 136
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#define FLASH_WAITSTATES (FLASH_ACR_LATENCY_4WS) /* 4 ws */
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#elif CLOCK_AHB >= 102
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#define FLASH_WAITSTATES (FLASH_ACR_LATENCY_3WS) /* 3 ws */
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#elif CLOCK_AHB >= 68
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#define FLASH_WAITSTATES (FLASH_ACR_LATENCY_2WS) /* 2 ws */
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#elif CLOCK_AHB >= 34
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#define FLASH_WAITSTATES (FLASH_ACR_LATENCY_1WS) /* 1 ws */
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#else
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#define FLASH_WAITSTATES (0) /* 0 ws */
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#endif
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void stmclk_init_sysclk(void)
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{
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/* disable any interrupts. Global interrupts could be enabled if this is
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* called from some kind of bootloader... */
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unsigned is = irq_disable();
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/* enable HSI clock for the duration of initialization */
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stmclk_enable_hsi();
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RCC->CIER = 0;
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/* use HSI as system clock while we do any further configuration and
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* configure the AHB and APB clock dividers as configured by the board */
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RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV);
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {}
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/* we enable I+D caches, pre-fetch, and we set the actual number of
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* needed flash wait states */
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FLASH->ACR |= (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN |
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FLASH_WAITSTATES);
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/* disable all active clocks except HSI -> resets the clk configuration */
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RCC->CR = RCC_CR_HSION;
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#if CLOCK_LSE
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stmclk_enable_lfclk();
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#endif
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#if CLOCK_USE_HSE
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/* if configured, we need to enable the HSE clock now */
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR & RCC_CR_HSERDY)) {}
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RCC->CFGR = (RCC_CFGR_SW_HSE | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV);
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSE) {}
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#elif CLOCK_USE_PLL
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#if CLOCK_HSE
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/* if configured, we need to enable the HSE clock now */
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR & RCC_CR_HSERDY)) {}
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#endif
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/* now we can safely configure and start the PLL */
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RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_R | RCC_PLLCFGR_PLLREN);
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY)) {}
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/* now that the PLL is running, we use it as system clock */
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
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#endif
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stmclk_disable_hsi();
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irq_restore(is);
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#ifdef MODULE_PERIPH_HWRNG
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/* HWRNG is clocked by HSI48 so enable this clock when the peripheral is used */
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RCC->CRRCR |= RCC_CRRCR_HSI48ON;
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while (!(RCC->CRRCR & RCC_CRRCR_HSI48RDY)) {}
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#endif
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#ifdef MODULE_PERIPH_RTT
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/* Ensure LPTIM1 clock source (LSI or LSE) is correctly reset when initializing
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the clock, this is particularly useful after waking up from deep sleep */
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#if CLOCK_LSE
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RCC->CCIPR |= RCC_CCIPR_LPTIM1SEL_0 | RCC_CCIPR_LPTIM1SEL_1;
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#else
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RCC->CCIPR |= RCC_CCIPR_LPTIM1SEL_0;
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#endif /* CLOCK_LSE */
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#endif /* MODULE_PERIPH_RTT */
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}
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