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https://github.com/RIOT-OS/RIOT.git
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335 lines
8.4 KiB
C
335 lines
8.4 KiB
C
/*
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* Copyright(C) 2017 Imagination Technologies Limited and/or its
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* affiliated group companies.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*
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*/
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/**
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* @ingroup cpu_mips_pic32_common
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* @ingroup drivers_periph_gpio
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* @{
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*
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* @file
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* @brief Low-level GPIO driver implementation
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*
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* @}
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*/
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#include "cpu.h"
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#include "eic.h"
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#include "periph/gpio.h"
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#include "periph_conf.h"
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#define LATx(P) ((P)[0x30/0x4])
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#define LATxCLR(P) ((P)[0x34/0x4])
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#define LATxSET(P) ((P)[0x38/0x4])
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#define LATxINV(P) ((P)[0x3C/0x4])
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#define PORTx(P) ((P)[0x20/0x4])
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#define CNPUxCLR(P) ((P)[0x54/0x4])
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#define CNPUxSET(P) ((P)[0x58/0x4])
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#define CNPDxCLR(P) ((P)[0x64/0x4])
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#define CNPDxSET(P) ((P)[0x68/0x4])
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#define ODCxCLR(P) ((P)[0x44/0x4])
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#define ODCxSET(P) ((P)[0x48/0x4])
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#define ANSELxCLR(P) ((P)[0x04/0x4])
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#define TRISxCLR(P) ((P)[0x14/0x4])
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#define TRISxSET(P) ((P)[0x18/0x4])
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#define CNENxCLR(P) ((P)[0x84/0x4])
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#define CNENxSET(P) ((P)[0x88/0x4])
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#define CNNExCLR(P) ((P)[0xA4/0x4])
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#define CNNExSET(P) ((P)[0xA8/0x4])
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#define CNSTATx(P) ((P)[0x90/0x4])
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#define CNCONxCLR(P) ((P)[0x74/0x4])
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#define CNCONxSET(P) ((P)[0x78/0x4])
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#define CNFx(P) ((P)[0xB0/0x4])
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/**
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* @brief Extract the port base address from the given pin identifier
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*/
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static inline volatile unsigned int * _port(gpio_t pin)
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{
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return (volatile unsigned int *)(pin & ~(0xff));
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}
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/**
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* @brief Extract the port number form the given identifier
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*
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* The port number is extracted by looking at bits 8, 9, 10, 11 of the base
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* register addresses.
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*/
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static inline int _port_num(gpio_t pin)
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{
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return ((pin >> 8) & 0x0f);
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}
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/**
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* @brief Extract the pin number from the last 4 bit of the pin identifier
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*/
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static inline int _pin_num(gpio_t pin)
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{
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return (pin & 0x0f);
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}
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#ifdef MODULE_PERIPH_GPIO_IRQ
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/**
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* @brief The PIC32 family has 7 I/O ports and 16 I/O per port
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*/
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#define PORT_NUMOF (7U)
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#define GPIO_NUMOF (16U)
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static gpio_flank_t isr_flank[PORT_NUMOF][GPIO_NUMOF];
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static gpio_isr_ctx_t isr_ctx[PORT_NUMOF][GPIO_NUMOF];
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#if defined(CPU_FAM_PIC32MX)
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static void isr_handler(uint32_t port_addr)
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{
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uint32_t cnstat = CNSTATx(_port(port_addr));
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cnstat &= (1 << GPIO_NUMOF) - 1;
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while (cnstat) {
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/* we want the position of the first one bit, so N_bits - (N_zeros + 1) */
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int pin = 32 - __builtin_clz(cnstat) - 1;
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uint32_t port = PORTx(_port(port_addr));
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cnstat &= ~(1 << pin);
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if (isr_flank[_port_num(port_addr)][pin] == GPIO_BOTH
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|| (isr_flank[_port_num(port_addr)][pin] == GPIO_RISING && (port & (1U << pin)))
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|| (isr_flank[_port_num(port_addr)][pin] == GPIO_FALLING && !(port & (1U << pin))))
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isr_ctx[_port_num(port_addr)][pin].cb(isr_ctx[_port_num(port_addr)][pin].arg);
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}
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}
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static void cn_isr(void)
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{
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#ifdef _PORTA_BASE_ADDRESS
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isr_handler(_PORTA_BASE_ADDRESS);
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#endif
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#ifdef _PORTB_BASE_ADDRESS
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isr_handler(_PORTB_BASE_ADDRESS);
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#endif
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#ifdef _PORTC_BASE_ADDRESS
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isr_handler(_PORTC_BASE_ADDRESS);
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#endif
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#ifdef _PORTD_BASE_ADDRESS
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isr_handler(_PORTD_BASE_ADDRESS);
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#endif
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#ifdef _PORTE_BASE_ADDRESS
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isr_handler(_PORTE_BASE_ADDRESS);
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#endif
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#ifdef _PORTF_BASE_ADDRESS
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isr_handler(_PORTF_BASE_ADDRESS);
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#endif
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#ifdef _PORTG_BASE_ADDRESS
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isr_handler(_PORTG_BASE_ADDRESS);
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#endif
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mips32r2_isr_end();
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}
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#elif defined(CPU_FAM_PIC32MZ)
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static void isr_handler(uint32_t port_addr)
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{
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while (CNFx(_port(port_addr))) {
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/* we want the position of the first one bit, so N_bits - (N_zeros + 1) */
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int pin = 32 - __builtin_clz(CNFx(_port(port_addr))) - 1;
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isr_ctx[_port_num(port_addr)][pin].cb(isr_ctx[_port_num(port_addr)][pin].arg);
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CNFx(_port(port_addr)) &= ~(1U << pin);
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}
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}
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static void cn_porta_isr(void)
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{
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isr_handler(_PORTA_BASE_ADDRESS);
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mips32r2_isr_end();
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}
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static void cn_portb_isr(void)
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{
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isr_handler(_PORTB_BASE_ADDRESS);
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mips32r2_isr_end();
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}
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static void cn_portc_isr(void)
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{
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isr_handler(_PORTC_BASE_ADDRESS);
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mips32r2_isr_end();
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}
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static void cn_portd_isr(void)
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{
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isr_handler(_PORTD_BASE_ADDRESS);
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mips32r2_isr_end();
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}
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static void cn_porte_isr(void)
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{
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isr_handler(_PORTE_BASE_ADDRESS);
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mips32r2_isr_end();
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}
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static void cn_portf_isr(void)
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{
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isr_handler(_PORTF_BASE_ADDRESS);
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mips32r2_isr_end();
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}
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static void cn_portg_isr(void)
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{
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isr_handler(_PORTG_BASE_ADDRESS);
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mips32r2_isr_end();
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}
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#endif
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#endif /* MODULE_PERIPH_GPIO_IRQ */
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int gpio_init(gpio_t pin, gpio_mode_t mode)
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{
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volatile unsigned int * port = _port(pin);
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int pin_num = _pin_num(pin);
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uint8_t output = 0, pu = 0, pd = 0, od = 0;
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switch (mode) {
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case GPIO_IN:
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break;
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case GPIO_IN_PD:
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pd = 1;
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break;
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case GPIO_IN_PU:
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pu = 1;
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break;
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case GPIO_OD_PU:
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pu = 1; /* fall-through */
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case GPIO_OD:
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od = 1; /* fall-through */
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case GPIO_OUT:
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output = 1;
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break;
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}
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ANSELxCLR(port) = 1U << pin_num; /* Configure GPIO as digital */
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if (pu)
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CNPUxSET(port) = 1U << pin_num;
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else
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CNPUxCLR(port) = 1U << pin_num;
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if (pd)
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CNPDxSET(port) = 1U << pin_num;
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else
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CNPDxCLR(port) = 1U << pin_num;
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if (od)
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ODCxSET(port) = 1U << pin_num;
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else
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ODCxCLR(port) = 1U << pin_num;
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if (output)
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TRISxCLR(port) = 1U << pin_num;
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else
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TRISxSET(port) = 1U << pin_num;
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return 0;
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}
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int gpio_read(gpio_t pin)
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{
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return PORTx(_port(pin)) & (1U << _pin_num(pin));
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}
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void gpio_set(gpio_t pin)
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{
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LATxSET(_port(pin)) = 1U << _pin_num(pin);
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}
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void gpio_clear(gpio_t pin)
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{
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LATxCLR(_port(pin)) = 1U << _pin_num(pin);
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}
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void gpio_toggle(gpio_t pin)
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{
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LATxINV(_port(pin)) = 1U << _pin_num(pin);
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}
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void gpio_write(gpio_t pin, int value)
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{
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if (value)
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gpio_set(pin);
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else
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gpio_clear(pin);
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}
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#ifdef MODULE_PERIPH_GPIO_IRQ
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int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
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gpio_cb_t cb, void *arg)
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{
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int pin_num = _pin_num(pin);
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int port_num = _port_num(pin);
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/* set callback */
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isr_ctx[port_num][pin_num].cb = cb;
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isr_ctx[port_num][pin_num].arg = arg;
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isr_flank[port_num][pin_num] = flank;
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/* initialize pin as input */
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gpio_init(pin, mode);
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#if defined(CPU_FAM_PIC32MX)
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set_external_isr_cb(_CHANGE_NOTICE_VECTOR, cn_isr);
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eic_configure_priority(_CHANGE_NOTICE_VECTOR, 1, 0);
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eic_enable(_CHANGE_NOTICE_A_IRQ + port_num);
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#elif defined(CPU_FAM_PIC32MZ)
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switch (port_num) {
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case PORT_A: set_external_isr_cb(_CHANGE_NOTICE_A_VECTOR, cn_porta_isr); break;
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case PORT_B: set_external_isr_cb(_CHANGE_NOTICE_B_VECTOR, cn_portb_isr); break;
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case PORT_C: set_external_isr_cb(_CHANGE_NOTICE_C_VECTOR, cn_portc_isr); break;
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case PORT_D: set_external_isr_cb(_CHANGE_NOTICE_D_VECTOR, cn_portd_isr); break;
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case PORT_E: set_external_isr_cb(_CHANGE_NOTICE_E_VECTOR, cn_porte_isr); break;
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case PORT_F: set_external_isr_cb(_CHANGE_NOTICE_F_VECTOR, cn_portf_isr); break;
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case PORT_G: set_external_isr_cb(_CHANGE_NOTICE_G_VECTOR, cn_portg_isr); break;
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}
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eic_configure_priority(_CHANGE_NOTICE_A_VECTOR + port_num, 1, 0);
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eic_enable(_CHANGE_NOTICE_A_VECTOR + port_num);
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CNCONxSET(_port(pin)) = _CNCONB_EDGEDETECT_MASK;
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#endif
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CNCONxSET(_port(pin)) = _CNCONB_ON_MASK;
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gpio_irq_enable(pin);
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return 0;
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}
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void gpio_irq_enable(gpio_t pin)
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{
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#if defined(CPU_FAM_PIC32MX)
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CNENxSET(_port(pin)) = 1U << _pin_num(pin);
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#elif defined(CPU_FAM_PIC32MZ)
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switch (isr_flank[_port_num(pin)][_pin_num(pin)]) {
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case GPIO_RISING:
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CNENxSET(_port(pin)) = 1U << _pin_num(pin);
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CNNExCLR(_port(pin)) = 1U << _pin_num(pin);
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break;
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case GPIO_FALLING:
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CNENxCLR(_port(pin)) = 1U << _pin_num(pin);
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CNNExSET(_port(pin)) = 1U << _pin_num(pin);
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break;
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case GPIO_BOTH:
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CNENxSET(_port(pin)) = 1U << _pin_num(pin);
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CNNExSET(_port(pin)) = 1U << _pin_num(pin);
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break;
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}
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#endif
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}
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void gpio_irq_disable(gpio_t pin)
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{
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CNENxCLR(_port(pin)) = 1U << _pin_num(pin);
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#if defined(CPU_FAM_PIC32Mz)
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CNNExCLR(_port(pin)) = 1U << _pin_num(pin);
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#endif
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}
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#endif /* MODULE_PERIPH_GPIO_IRQ */
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