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72 lines
2.1 KiB
C
72 lines
2.1 KiB
C
/*
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* Copyright (C) 2016 Kaspar Schleiser <kaspar@schleiser.de>
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* 2015 Freie Universität Berlin
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* 2015 Engineering-Spirit
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Implementation of the kernels power management interface
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*
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* @author Nick v. IJzendoorn <nijzndoorn@engineering-spirit.nl>
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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* @author Fabian Nack <nack@inf.fu-berlin.de>
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*
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* @}
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*/
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#include "irq.h"
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#include "periph/pm.h"
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#define ENABLE_DEBUG (1)
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#include "debug.h"
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void pm_set(unsigned mode)
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{
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/* I just copied it from stm32f1/2/4, but I suppose it would work for the
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* others... /KS */
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#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
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switch (mode) {
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case 0:
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/* Set PDDS to enter standby mode on deepsleep and clear flags */
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PWR->CR |= (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF);
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/* Enable WKUP pin to use for wakeup from standby mode */
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PWR->CSR |= PWR_CSR_EWUP;
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/* Set SLEEPDEEP bit of system control block */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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break;
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case 1: /* STM Stop mode */
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/* Clear PDDS and LPDS bits to enter stop mode on */
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/* deepsleep with voltage regulator on */
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PWR->CR &= ~(PWR_CR_PDDS | PWR_CR_LPDS);
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/* Set SLEEPDEEP bit of system control block */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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break;
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case 2: /* STM Sleep mode */
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/* Reset SLEEPDEEP bit of system control block */
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SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk);
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break;
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}
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#endif
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/* Executes a device DSB (Data Synchronization Barrier) */
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__DSB();
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/* Enter standby mode */
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__WFI();
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}
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#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
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void pm_off(void)
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{
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irq_disable();
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pm_set(0);
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}
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#endif
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