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126 lines
3.2 KiB
C
126 lines
3.2 KiB
C
/*
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* ssp0-borad.h - header file of the SPI interface for the LPC2387.
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* Copyright (C) 2013 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*
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*/
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/**
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* @file
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* @internal
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* @brief SPI interface definitions for the LPC2387
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*
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* @author Marco Ziegert <ziegert@inf.fu-berlin.de>
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* @author Zakaria Kasmi <zkasmi@inf.fu-berlin.de>
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* @version $Revision: 3854 $
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*
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* @note $Id: avsextrem-ssp0.c 3854 2010-01-18 15:27:01Z zkasmi $
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*/
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#ifndef SSP_H_
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#define SSP_H_
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#include "stdint.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define DMA_ENABLED 0
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/*
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* if USE_CS is zero, set SSEL as GPIO that you have total control of the
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* sequence
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**/
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#define USE_CS 0
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/*
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* if 1, use driver for onboard BMA180, otherwise for external BMA180 utilizing
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* Nanopan Connector
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**/
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#define BMA180_ONBOARD 1
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#define SMB380_ACC 0
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#define NANOPAN 1
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#define NORDIC 2
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#define BMA180_EXTERN 3
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#define BMA180_INTERN 4
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#define L3G_EXTERN 5
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#define L3G_INTERN 6
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#define ACAMDMS 7
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/* SPI read and write buffer size */
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#define BUFSIZE 256
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#define FIFOSIZE 8
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/* SSP select pin */
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#define SSP0_SEL 1 << 21 /* P1.21 SMB380 */
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#define SSP0_SELN 1 << 16 /* P0.16 Nanotron */
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/* SSP1 external interrupt Pin (SMB380 specific) */
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#define SMB380_INT1 1 << 1 /* P0.1 */
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#define BMA180_INT1 1 << 8 /* P2.8 */
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/* SSP1 CR0 register */
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#define SSPCR0_DSS 1 << 0
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#define SSPCR0_FRF 1 << 4
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#define SSPCR0_SPO 1 << 6
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#define SSPCR0_SPH 1 << 7
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#define SSPCR0_SCR 1 << 8
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/* SSP1 CR1 register */
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#define SSPCR1_LBM 1 << 0
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#define SSPCR1_SSE 1 << 1
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#define SSPCR1_MS 1 << 2
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#define SSPCR1_SOD 1 << 3
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/* SSP1 Interrupt Mask Set/Clear register */
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#define SSPIMSC_RORIM 1 << 0
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#define SSPIMSC_RTIM 1 << 1
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#define SSPIMSC_RXIM 1 << 2
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#define SSPIMSC_TXIM 1 << 3
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/* SSP1 Interrupt Status register */
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#define SSPRIS_RORRIS 1 << 0
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#define SSPRIS_RTRIS 1 << 1
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#define SSPRIS_RXRIS 1 << 2
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#define SSPRIS_TXRIS 1 << 3
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/* SSP1 Masked Interrupt register */
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#define SSPMIS_RORMIS 1 << 0
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#define SSPMIS_RTMIS 1 << 1
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#define SSPMIS_RXMIS 1 << 2
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#define SSPMIS_TXMIS 1 << 3
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/* SSP1 Interrupt clear register */
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#define SSPICR_RORIC 1 << 0
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#define SSPICR_RTIC 1 << 1
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#define SSP1_INTERRUPT_MODE 0
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#define SMB380_EXTINT_MODE 1
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#define BMA180_EXTINT_MODE 1
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uint32_t SSP0Init(void);
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uint8_t SSP0Prepare(uint8_t chip, uint8_t datasize, uint8_t cpol, uint8_t cpha,
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uint16_t freq);
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uint8_t SSP0Unprepare(uint8_t chip);
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unsigned char SSP0_write(const uint16_t data, uint8_t device);
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unsigned short SSP0_read(uint8_t device);
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unsigned char SMB380_ssp_write(const unsigned char regAddr,
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const unsigned char data, unsigned char flag);
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unsigned short SMB380_ssp_read(void);
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unsigned short nrf24l01_ssp_read_write(const uint8_t data);
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unsigned short acam_trx(const uint8_t data);
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void SSP0Handler(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* SSP_H_ */
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