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122 lines
4.2 KiB
Plaintext
122 lines
4.2 KiB
Plaintext
;
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; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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;
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; SPDX-License-Identifier: BSD-3-Clause
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;
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.program i2c
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.side_set 1 opt pindirs
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; TX Encoding:
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; | 15:10 | 9 | 8:1 | 0 |
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; | Instr | Final | Data | NAK |
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;
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; If Instr has a value n > 0, then this FIFO word has no
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; data payload, and the next n + 1 words will be executed as instructions.
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; Otherwise, shift out the 8 data bits, followed by the ACK bit.
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;
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; The Instr mechanism allows stop/start/repstart sequences to be programmed
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; by the processor, and then carried out by the state machine at defined points
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; in the datastream.
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;
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; The "Final" field should be set for the final byte in a transfer.
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; This tells the state machine to ignore a NAK: if this field is not
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; set, then any NAK will cause the state machine to halt and interrupt.
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;
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; Autopull should be enabled, with a threshold of 16.
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; Autopush should be enabled, with a threshold of 8.
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; The TX FIFO should be accessed with halfword writes, to ensure
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; the data is immediately available in the OSR.
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;
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; Pin mapping:
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; - Input pin 0 is SDA, 1 is SCL (if clock stretching used)
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; - Jump pin is SDA
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; - Side-set pin 0 is SCL
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; - Set pin 0 is SDA
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; - OUT pin 0 is SDA
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; - SCL must be SDA + 1 (for wait mapping)
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;
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; The OE outputs should be inverted in the system IO controls!
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; (It's possible for the inversion to be done in this program,
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; but costs 2 instructions: 1 for inversion, and one to cope
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; with the side effect of the MOV on TX shift counter.)
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do_nack:
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jmp y-- entry_point ; Continue if NAK was expected
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irq wait 0 rel ; Otherwise stop, ask for help
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do_byte:
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set x, 7 ; Loop 8 times
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bitloop:
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out pindirs, 1 [7] ; Serialise write data (all-ones if reading)
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nop side 1 [2] ; SCL rising edge
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wait 1 pin, 1 [4] ; Allow clock to be stretched
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in pins, 1 [7] ; Sample read data in middle of SCL pulse
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jmp x-- bitloop side 0 [7] ; SCL falling edge
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; Handle ACK pulse
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out pindirs, 1 [7] ; On reads, we provide the ACK.
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nop side 1 [7] ; SCL rising edge
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wait 1 pin, 1 [7] ; Allow clock to be stretched
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jmp pin do_nack side 0 [2] ; Test SDA for ACK/NAK, fall through if ACK
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public entry_point:
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.wrap_target
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out x, 6 ; Unpack Instr count
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out y, 1 ; Unpack the NAK ignore bit
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jmp !x do_byte ; Instr == 0, this is a data record.
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out null, 32 ; Instr > 0, remainder of this OSR is invalid
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do_exec:
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out exec, 16 ; Execute one instruction per FIFO word
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jmp x-- do_exec ; Repeat n + 1 times
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.wrap
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% c-sdk {
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#include "hardware/clocks.h"
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#include "hardware/gpio.h"
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static inline void i2c_program_init(PIO pio, uint sm, uint offset, uint pin_sda, uint pin_scl) {
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assert(pin_scl == pin_sda + 1);
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pio_sm_config c = i2c_program_get_default_config(offset);
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// IO mapping
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sm_config_set_out_pins(&c, pin_sda, 1);
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sm_config_set_set_pins(&c, pin_sda, 1);
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sm_config_set_in_pins(&c, pin_sda);
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sm_config_set_sideset_pins(&c, pin_scl);
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sm_config_set_jmp_pin(&c, pin_sda);
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sm_config_set_out_shift(&c, false, true, 16);
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sm_config_set_in_shift(&c, false, true, 8);
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float div = (float)clock_get_hz(clk_sys) / (32 * 100000);
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sm_config_set_clkdiv(&c, div);
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// Try to avoid glitching the bus while connecting the IOs. Get things set
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// up so that pin is driven down when PIO asserts OE low, and pulled up
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// otherwise.
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gpio_pull_up(pin_scl);
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gpio_pull_up(pin_sda);
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uint32_t both_pins = (1u << pin_sda) | (1u << pin_scl);
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pio_sm_set_pins_with_mask(pio, sm, both_pins, both_pins);
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pio_sm_set_pindirs_with_mask(pio, sm, both_pins, both_pins);
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pio_gpio_init(pio, pin_sda);
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gpio_set_oeover(pin_sda, GPIO_OVERRIDE_INVERT);
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pio_gpio_init(pio, pin_scl);
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gpio_set_oeover(pin_scl, GPIO_OVERRIDE_INVERT);
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pio_sm_set_pins_with_mask(pio, sm, 0, both_pins);
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// Clear IRQ flag before starting
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hw_clear_bits(&pio->inte0, 1u << sm);
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hw_clear_bits(&pio->inte1, 1u << sm);
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pio->irq = 1u << sm;
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// Configure and start SM
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pio_sm_init(pio, sm, offset + i2c_offset_entry_point, &c);
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pio_sm_set_enabled(pio, sm, true);
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}
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%}
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