mirror of
https://github.com/RIOT-OS/RIOT.git
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203 lines
5.7 KiB
C
203 lines
5.7 KiB
C
/*
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* Copyright (C) 2014 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @defgroup board_mulle Eistec Mulle
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* @ingroup boards
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* @brief Board specific files for Eistec Mulle IoT boards
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* @{
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*
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* @file
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* @brief Board specific definitions for the Eistec Mulle IoT board
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#include "cpu.h"
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#include "periph_conf.h"
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#include "mulle-nvram.h"
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#include "mtd.h"
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/* Use the on board RTC 32kHz clock for LPTMR clocking. */
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#undef LPTIMER_CLKSRC
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/** @brief Clock source for the LPTMR module */
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#define LPTIMER_CLKSRC LPTIMER_CLKSRC_ERCLK32K
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/** Disable hardware watchdog, for debugging purposes, don't use this on production builds. */
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#define DISABLE_WDOG 1
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/**
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* @brief xtimer configuration
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* @{
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*/
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#if 0
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/* LPTMR xtimer configuration */
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/* WIP, Use PIT for now */
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#define XTIMER_DEV (TIMER_LPTMR_DEV(0))
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#define XTIMER_CHAN (0)
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/* LPTMR is 16 bits wide */
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#define XTIMER_WIDTH (16)
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#define XTIMER_BACKOFF (4)
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#define XTIMER_ISR_BACKOFF (4)
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#define XTIMER_OVERHEAD (3)
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#define XTIMER_HZ (32768ul)
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#define XTIMER_SHIFT (0)
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#else
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/* PIT xtimer configuration */
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#define XTIMER_DEV (TIMER_PIT_DEV(0))
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#define XTIMER_CHAN (0)
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#define XTIMER_WIDTH (32)
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#define XTIMER_BACKOFF (40)
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#define XTIMER_ISR_BACKOFF (40)
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#define XTIMER_OVERHEAD (30)
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#define XTIMER_HZ (1000000ul)
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#define XTIMER_SHIFT (0)
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#endif
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/** @} */
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/**
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* @brief LED pin definitions and handlers
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* @{
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*/
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#define LED_PORT PTC
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#define LED0_BIT (15)
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#define LED1_BIT (14)
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#define LED2_BIT (13)
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#define LED0_PIN GPIO_PIN(PORT_C, LED0_BIT)
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#define LED1_PIN GPIO_PIN(PORT_C, LED1_BIT)
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#define LED2_PIN GPIO_PIN(PORT_C, LED2_BIT)
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#define LED0_ON (BITBAND_REG32(LED_PORT->PSOR, LED0_BIT) = 1)
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#define LED0_OFF (BITBAND_REG32(LED_PORT->PCOR, LED0_BIT) = 1)
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#define LED0_TOGGLE (BITBAND_REG32(LED_PORT->PTOR, LED0_BIT) = 1)
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#define LED1_ON (BITBAND_REG32(LED_PORT->PSOR, LED1_BIT) = 1)
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#define LED1_OFF (BITBAND_REG32(LED_PORT->PCOR, LED1_BIT) = 1)
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#define LED1_TOGGLE (BITBAND_REG32(LED_PORT->PTOR, LED1_BIT) = 1)
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#define LED2_ON (BITBAND_REG32(LED_PORT->PSOR, LED2_BIT) = 1)
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#define LED2_OFF (BITBAND_REG32(LED_PORT->PCOR, LED2_BIT) = 1)
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#define LED2_TOGGLE (BITBAND_REG32(LED_PORT->PTOR, LED2_BIT) = 1)
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/** @} */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Initialize board specific hardware, including clock, LEDs and std-IO
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*/
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void board_init(void);
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#ifdef __cplusplus
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}
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#endif
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/**
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* @name Define the interface to the AT86RF212B radio
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*
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* @todo Work around missing RESET pin on Mulle v0.6x
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*
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* {spi bus, spi speed, cs pin, int pin, reset pin, sleep pin}
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*/
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#define AT86RF2XX_PARAMS_BOARD {.spi = SPI_DEV(0), \
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.spi_clk = SPI_CLK_5MHZ, \
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.cs_pin = SPI_HWCS(1), \
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.int_pin = GPIO_PIN(PORT_B, 9), \
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.sleep_pin = GPIO_PIN(PORT_E, 6), \
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.reset_pin = GPIO_PIN(PORT_C, 12)}
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/**
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* @name LIS3DH configuration
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* @{
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*/
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#define LIS3DH_INT1 GPIO_PIN(PORT_C, 18)
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#define LIS3DH_INT2 GPIO_PIN(PORT_C, 17)
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#define LIS3DH_CS GPIO_PIN(PORT_D, 0)
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#define LIS3DH_CLK SPI_CLK_5MHZ
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#define LIS3DH_SPI SPI_DEV(0)
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/** @} */
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/**
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* @name Mulle power control configuration
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*/
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/** @{ */
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#define MULLE_POWER_AVDD GPIO_PIN(PORT_B, 17) /**< AVDD enable pin */
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#define MULLE_POWER_VPERIPH GPIO_PIN(PORT_D, 7) /**< VPERIPH enable pin */
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#define MULLE_POWER_VSEC GPIO_PIN(PORT_B, 16) /**< VSEC enable pin */
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/** @} */
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/**
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* @name Mulle NVRAM hardware configuration
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*/
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/** @{ */
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#define MULLE_NVRAM_SPI_DEV SPI_DEV(0)
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#define MULLE_NVRAM_SPI_CLK SPI_CLK_5MHZ
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#define MULLE_NVRAM_SPI_CS SPI_HWCS(3) /**< FRAM CS pin */
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#define MULLE_NVRAM_CAPACITY 512 /**< FRAM size, in bytes */
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#define MULLE_NVRAM_SPI_ADDRESS_COUNT 1 /**< FRAM addressing size, in bytes */
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/** @} */
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/**
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* @name Mulle NOR flash hardware configuration
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*/
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/** @{ */
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#define MULLE_NOR_SPI_DEV SPI_DEV(0)
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#define MULLE_NOR_SPI_CLK SPI_CLK_5MHZ
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#define MULLE_NOR_SPI_CS SPI_HWCS(2) /**< Flash CS pin */
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/** @} */
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/**
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* @name MTD configuration
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*/
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/** @{ */
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extern mtd_dev_t *mtd0;
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#define MTD_0 mtd0
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/** @} */
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/**
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* @name Mulle Vchr, Vbat ADC lines
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*/
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/** @{ */
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#define MULLE_VBAT_ADC_LINE ADC_LINE(6)
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#define MULLE_VCHR_ADC_LINE ADC_LINE(7)
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/** @} */
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/**
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* @name K60 clock dividers
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*/
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/** @{ */
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/**
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* System clock divider setting, the actual hardware register value, see reference manual for details.
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*/
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#define CONFIG_CLOCK_K60_SYS_DIV 0x00
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/**
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* Bus clock divider setting, the actual hardware register value, see reference manual for details
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*/
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#define CONFIG_CLOCK_K60_BUS_DIV 0x01
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/**
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* Flexbus clock divider setting, the actual hardware register value, see reference manual for details
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*/
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#define CONFIG_CLOCK_K60_FB_DIV 0x01
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/**
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* Flash clock divider setting, the actual hardware register value, see reference manual for details
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*/
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#define CONFIG_CLOCK_K60_FLASH_DIV 0x03
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/** @} */
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#endif /* BOARD_H */
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/** @} */
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