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545 lines
26 KiB
C
545 lines
26 KiB
C
/******************************************************************************
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* Filename: hw_ssi_h
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* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017)
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* Revision: 48345
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_SSI_H__
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#define __HW_SSI_H__
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//*****************************************************************************
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//
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// This section defines the register offsets of
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// SSI component
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//
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//*****************************************************************************
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// Control 0
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#define SSI_O_CR0 0x00000000
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// Control 1
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#define SSI_O_CR1 0x00000004
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// Data
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#define SSI_O_DR 0x00000008
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// Status
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#define SSI_O_SR 0x0000000C
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// Clock Prescale
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#define SSI_O_CPSR 0x00000010
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// Interrupt Mask Set and Clear
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#define SSI_O_IMSC 0x00000014
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// Raw Interrupt Status
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#define SSI_O_RIS 0x00000018
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// Masked Interrupt Status
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#define SSI_O_MIS 0x0000001C
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// Interrupt Clear
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#define SSI_O_ICR 0x00000020
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// DMA Control
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#define SSI_O_DMACR 0x00000024
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//*****************************************************************************
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//
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// Register: SSI_O_CR0
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//
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//*****************************************************************************
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// Field: [15:8] SCR
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//
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// Serial clock rate:
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// This is used to generate the transmit and receive bit rate of the SSI. The
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// bit rate is
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// (SSI's clock frequency)/((SCR+1)*CPSR.CPSDVSR).
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// SCR is a value from 0-255.
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#define SSI_CR0_SCR_W 8
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#define SSI_CR0_SCR_M 0x0000FF00
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#define SSI_CR0_SCR_S 8
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// Field: [7] SPH
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//
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// CLKOUT phase (Motorola SPI frame format only)
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// This bit selects the clock edge that captures data and enables it to change
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// state. It
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// has the most impact on the first bit transmitted by either permitting or not
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// permitting a clock transition before the first data capture edge.
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// ENUMs:
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// 2ND_CLK_EDGE Data is captured on the second clock edge
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// transition.
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// 1ST_CLK_EDGE Data is captured on the first clock edge
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// transition.
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#define SSI_CR0_SPH 0x00000080
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#define SSI_CR0_SPH_BITN 7
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#define SSI_CR0_SPH_M 0x00000080
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#define SSI_CR0_SPH_S 7
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#define SSI_CR0_SPH_2ND_CLK_EDGE 0x00000080
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#define SSI_CR0_SPH_1ST_CLK_EDGE 0x00000000
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// Field: [6] SPO
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//
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// CLKOUT polarity (Motorola SPI frame format only)
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// ENUMs:
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// HIGH SSI produces a steady state HIGH value on the
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// CLKOUT pin when data is not being transferred.
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// LOW SSI produces a steady state LOW value on the
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// CLKOUT pin when data is
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// not being transferred.
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#define SSI_CR0_SPO 0x00000040
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#define SSI_CR0_SPO_BITN 6
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#define SSI_CR0_SPO_M 0x00000040
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#define SSI_CR0_SPO_S 6
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#define SSI_CR0_SPO_HIGH 0x00000040
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#define SSI_CR0_SPO_LOW 0x00000000
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// Field: [5:4] FRF
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//
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// Frame format.
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// The supported frame formats are Motorola SPI, TI synchronous serial and
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// National Microwire.
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// Value 0'b11 is reserved and shall not be used.
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// ENUMs:
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// NATIONAL_MICROWIRE National Microwire frame format
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// TI_SYNC_SERIAL TI synchronous serial frame format
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// MOTOROLA_SPI Motorola SPI frame format
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#define SSI_CR0_FRF_W 2
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#define SSI_CR0_FRF_M 0x00000030
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#define SSI_CR0_FRF_S 4
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#define SSI_CR0_FRF_NATIONAL_MICROWIRE 0x00000020
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#define SSI_CR0_FRF_TI_SYNC_SERIAL 0x00000010
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#define SSI_CR0_FRF_MOTOROLA_SPI 0x00000000
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// Field: [3:0] DSS
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//
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// Data Size Select.
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// Values 0b0000, 0b0001, 0b0010 are reserved and shall not be used.
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// ENUMs:
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// 16_BIT 16-bit data
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// 15_BIT 15-bit data
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// 14_BIT 14-bit data
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// 13_BIT 13-bit data
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// 12_BIT 12-bit data
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// 11_BIT 11-bit data
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// 10_BIT 10-bit data
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// 9_BIT 9-bit data
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// 8_BIT 8-bit data
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// 7_BIT 7-bit data
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// 6_BIT 6-bit data
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// 5_BIT 5-bit data
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// 4_BIT 4-bit data
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#define SSI_CR0_DSS_W 4
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#define SSI_CR0_DSS_M 0x0000000F
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#define SSI_CR0_DSS_S 0
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#define SSI_CR0_DSS_16_BIT 0x0000000F
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#define SSI_CR0_DSS_15_BIT 0x0000000E
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#define SSI_CR0_DSS_14_BIT 0x0000000D
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#define SSI_CR0_DSS_13_BIT 0x0000000C
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#define SSI_CR0_DSS_12_BIT 0x0000000B
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#define SSI_CR0_DSS_11_BIT 0x0000000A
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#define SSI_CR0_DSS_10_BIT 0x00000009
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#define SSI_CR0_DSS_9_BIT 0x00000008
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#define SSI_CR0_DSS_8_BIT 0x00000007
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#define SSI_CR0_DSS_7_BIT 0x00000006
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#define SSI_CR0_DSS_6_BIT 0x00000005
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#define SSI_CR0_DSS_5_BIT 0x00000004
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#define SSI_CR0_DSS_4_BIT 0x00000003
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//*****************************************************************************
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//
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// Register: SSI_O_CR1
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//
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//*****************************************************************************
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// Field: [3] SOD
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//
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// Slave-mode output disabled
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// This bit is relevant only in the slave mode, MS=1. In multiple-slave
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// systems, it is possible for an SSI master to broadcast a message to all
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// slaves in the system while ensuring that only one slave drives data onto its
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// serial output line. In such systems the RXD lines from multiple slaves could
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// be tied together. To operate in such systems, this bitfield can be set if
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// the SSI slave is not supposed to drive the TXD line:
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//
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// 0: SSI can drive the TXD output in slave mode.
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// 1: SSI cannot drive the TXD output in slave mode.
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#define SSI_CR1_SOD 0x00000008
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#define SSI_CR1_SOD_BITN 3
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#define SSI_CR1_SOD_M 0x00000008
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#define SSI_CR1_SOD_S 3
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// Field: [2] MS
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//
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// Master or slave mode select. This bit can be modified only when SSI is
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// disabled, SSE=0.
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// ENUMs:
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// SLAVE Device configured as slave
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// MASTER Device configured as master
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#define SSI_CR1_MS 0x00000004
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#define SSI_CR1_MS_BITN 2
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#define SSI_CR1_MS_M 0x00000004
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#define SSI_CR1_MS_S 2
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#define SSI_CR1_MS_SLAVE 0x00000004
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#define SSI_CR1_MS_MASTER 0x00000000
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// Field: [1] SSE
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//
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// Synchronous serial interface enable.
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// ENUMs:
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// SSI_ENABLED Operation enabled
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// SSI_DISABLED Operation disabled
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#define SSI_CR1_SSE 0x00000002
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#define SSI_CR1_SSE_BITN 1
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#define SSI_CR1_SSE_M 0x00000002
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#define SSI_CR1_SSE_S 1
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#define SSI_CR1_SSE_SSI_ENABLED 0x00000002
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#define SSI_CR1_SSE_SSI_DISABLED 0x00000000
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// Field: [0] LBM
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//
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// Loop back mode:
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//
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// 0: Normal serial port operation enabled.
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// 1: Output of transmit serial shifter is connected to input of receive serial
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// shifter internally.
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#define SSI_CR1_LBM 0x00000001
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#define SSI_CR1_LBM_BITN 0
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#define SSI_CR1_LBM_M 0x00000001
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#define SSI_CR1_LBM_S 0
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//*****************************************************************************
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//
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// Register: SSI_O_DR
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//
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//*****************************************************************************
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// Field: [15:0] DATA
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//
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// Transmit/receive data
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// The values read from this field or written to this field must be
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// right-justified when SSI is programmed for a data size that is less than 16
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// bits (CR0.DSS != 0b1111). Unused bits at the top are ignored by transmit
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// logic. The receive logic automatically right-justifies.
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#define SSI_DR_DATA_W 16
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#define SSI_DR_DATA_M 0x0000FFFF
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#define SSI_DR_DATA_S 0
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//*****************************************************************************
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//
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// Register: SSI_O_SR
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//
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//*****************************************************************************
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// Field: [4] BSY
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//
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// Serial interface busy:
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//
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// 0: SSI is idle
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// 1: SSI is currently transmitting and/or receiving a frame or the transmit
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// FIFO is not empty.
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#define SSI_SR_BSY 0x00000010
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#define SSI_SR_BSY_BITN 4
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#define SSI_SR_BSY_M 0x00000010
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#define SSI_SR_BSY_S 4
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// Field: [3] RFF
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//
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// Receive FIFO full:
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//
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// 0: Receive FIFO is not full.
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// 1: Receive FIFO is full.
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#define SSI_SR_RFF 0x00000008
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#define SSI_SR_RFF_BITN 3
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#define SSI_SR_RFF_M 0x00000008
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#define SSI_SR_RFF_S 3
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// Field: [2] RNE
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//
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// Receive FIFO not empty
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//
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// 0: Receive FIFO is empty.
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// 1: Receive FIFO is not empty.
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#define SSI_SR_RNE 0x00000004
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#define SSI_SR_RNE_BITN 2
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#define SSI_SR_RNE_M 0x00000004
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#define SSI_SR_RNE_S 2
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// Field: [1] TNF
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//
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// Transmit FIFO not full:
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//
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// 0: Transmit FIFO is full.
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// 1: Transmit FIFO is not full.
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#define SSI_SR_TNF 0x00000002
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#define SSI_SR_TNF_BITN 1
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#define SSI_SR_TNF_M 0x00000002
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#define SSI_SR_TNF_S 1
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// Field: [0] TFE
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//
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// Transmit FIFO empty:
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//
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// 0: Transmit FIFO is not empty.
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// 1: Transmit FIFO is empty.
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#define SSI_SR_TFE 0x00000001
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#define SSI_SR_TFE_BITN 0
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#define SSI_SR_TFE_M 0x00000001
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#define SSI_SR_TFE_S 0
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//*****************************************************************************
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//
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// Register: SSI_O_CPSR
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//
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//*****************************************************************************
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// Field: [7:0] CPSDVSR
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//
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// Clock prescale divisor:
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// This field specifies the division factor by which the input system clock to
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// SSI must be internally divided before further use.
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// The value programmed into this field must be an even non-zero number
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// (2-254). The least significant bit of the programmed number is hard-coded to
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// zero. If an odd number is written to this register, data read back from
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// this register has the least significant bit as zero.
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#define SSI_CPSR_CPSDVSR_W 8
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#define SSI_CPSR_CPSDVSR_M 0x000000FF
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#define SSI_CPSR_CPSDVSR_S 0
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//*****************************************************************************
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//
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// Register: SSI_O_IMSC
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//
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//*****************************************************************************
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// Field: [3] TXIM
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//
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// Transmit FIFO interrupt mask:
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// A read returns the current mask for transmit FIFO interrupt. On a write of
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// 1, the mask for transmit FIFO interrupt is set which means the interrupt
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// state will be reflected in MIS.TXMIS. A write of 0 clears the mask which
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// means MIS.TXMIS will not reflect the interrupt.
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#define SSI_IMSC_TXIM 0x00000008
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#define SSI_IMSC_TXIM_BITN 3
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#define SSI_IMSC_TXIM_M 0x00000008
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#define SSI_IMSC_TXIM_S 3
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// Field: [2] RXIM
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//
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// Receive FIFO interrupt mask:
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// A read returns the current mask for receive FIFO interrupt. On a write of 1,
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// the mask for receive FIFO interrupt is set which means the interrupt state
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// will be reflected in MIS.RXMIS. A write of 0 clears the mask which means
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// MIS.RXMIS will not reflect the interrupt.
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#define SSI_IMSC_RXIM 0x00000004
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#define SSI_IMSC_RXIM_BITN 2
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#define SSI_IMSC_RXIM_M 0x00000004
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#define SSI_IMSC_RXIM_S 2
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// Field: [1] RTIM
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//
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// Receive timeout interrupt mask:
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// A read returns the current mask for receive timeout interrupt. On a write of
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// 1, the mask for receive timeout interrupt is set which means the interrupt
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// state will be reflected in MIS.RTMIS. A write of 0 clears the mask which
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// means MIS.RTMIS will not reflect the interrupt.
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#define SSI_IMSC_RTIM 0x00000002
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#define SSI_IMSC_RTIM_BITN 1
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#define SSI_IMSC_RTIM_M 0x00000002
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#define SSI_IMSC_RTIM_S 1
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// Field: [0] RORIM
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//
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// Receive overrun interrupt mask:
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// A read returns the current mask for receive overrun interrupt. On a write of
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// 1, the mask for receive overrun interrupt is set which means the interrupt
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// state will be reflected in MIS.RORMIS. A write of 0 clears the mask which
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// means MIS.RORMIS will not reflect the interrupt.
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#define SSI_IMSC_RORIM 0x00000001
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#define SSI_IMSC_RORIM_BITN 0
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#define SSI_IMSC_RORIM_M 0x00000001
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#define SSI_IMSC_RORIM_S 0
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//*****************************************************************************
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//
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// Register: SSI_O_RIS
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//
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//*****************************************************************************
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// Field: [3] TXRIS
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//
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// Raw transmit FIFO interrupt status:
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// The transmit interrupt is asserted when there are four or fewer valid
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// entries in the transmit FIFO. The transmit interrupt is not qualified with
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// the SSI enable signal. Therefore one of the following ways can be used:
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// - data can be written to the transmit FIFO prior to enabling the SSI and
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// the
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// interrupts.
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// - SSI and interrupts can be enabled so that data can be written to the
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// transmit FIFO by an interrupt service routine.
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#define SSI_RIS_TXRIS 0x00000008
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#define SSI_RIS_TXRIS_BITN 3
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#define SSI_RIS_TXRIS_M 0x00000008
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#define SSI_RIS_TXRIS_S 3
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// Field: [2] RXRIS
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//
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// Raw interrupt state of receive FIFO interrupt:
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// The receive interrupt is asserted when there are four or more valid entries
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// in the receive FIFO.
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#define SSI_RIS_RXRIS 0x00000004
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#define SSI_RIS_RXRIS_BITN 2
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#define SSI_RIS_RXRIS_M 0x00000004
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#define SSI_RIS_RXRIS_S 2
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// Field: [1] RTRIS
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//
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// Raw interrupt state of receive timeout interrupt:
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// The receive timeout interrupt is asserted when the receive FIFO is not empty
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// and SSI has remained idle for a fixed 32 bit period. This mechanism can be
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// used to notify the user that data is still present in the receive FIFO and
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// requires servicing. This interrupt is deasserted if the receive FIFO becomes
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// empty by subsequent reads, or if new data is received on RXD.
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// It can also be cleared by writing to ICR.RTIC.
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#define SSI_RIS_RTRIS 0x00000002
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#define SSI_RIS_RTRIS_BITN 1
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#define SSI_RIS_RTRIS_M 0x00000002
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#define SSI_RIS_RTRIS_S 1
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// Field: [0] RORRIS
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//
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// Raw interrupt state of receive overrun interrupt:
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// The receive overrun interrupt is asserted when the FIFO is already full and
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// an additional data frame is received, causing an overrun of the FIFO. Data
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// is over-written in the
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// receive shift register, but not the FIFO so the FIFO contents stay valid.
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// It can also be cleared by writing to ICR.RORIC.
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#define SSI_RIS_RORRIS 0x00000001
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#define SSI_RIS_RORRIS_BITN 0
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#define SSI_RIS_RORRIS_M 0x00000001
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#define SSI_RIS_RORRIS_S 0
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//*****************************************************************************
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//
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// Register: SSI_O_MIS
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//
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//*****************************************************************************
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// Field: [3] TXMIS
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//
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// Masked interrupt state of transmit FIFO interrupt:
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// This field returns the masked interrupt state of transmit FIFO interrupt
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// which is the AND product of raw interrupt state RIS.TXRIS and the mask
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// setting IMSC.TXIM.
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#define SSI_MIS_TXMIS 0x00000008
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#define SSI_MIS_TXMIS_BITN 3
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#define SSI_MIS_TXMIS_M 0x00000008
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#define SSI_MIS_TXMIS_S 3
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// Field: [2] RXMIS
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//
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// Masked interrupt state of receive FIFO interrupt:
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// This field returns the masked interrupt state of receive FIFO interrupt
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// which is the AND product of raw interrupt state RIS.RXRIS and the mask
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// setting IMSC.RXIM.
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#define SSI_MIS_RXMIS 0x00000004
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#define SSI_MIS_RXMIS_BITN 2
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#define SSI_MIS_RXMIS_M 0x00000004
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#define SSI_MIS_RXMIS_S 2
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|
|
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// Field: [1] RTMIS
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//
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// Masked interrupt state of receive timeout interrupt:
|
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// This field returns the masked interrupt state of receive timeout interrupt
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|
// which is the AND product of raw interrupt state RIS.RTRIS and the mask
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|
// setting IMSC.RTIM.
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|
#define SSI_MIS_RTMIS 0x00000002
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#define SSI_MIS_RTMIS_BITN 1
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#define SSI_MIS_RTMIS_M 0x00000002
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#define SSI_MIS_RTMIS_S 1
|
|
|
|
// Field: [0] RORMIS
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|
//
|
|
// Masked interrupt state of receive overrun interrupt:
|
|
// This field returns the masked interrupt state of receive overrun interrupt
|
|
// which is the AND product of raw interrupt state RIS.RORRIS and the mask
|
|
// setting IMSC.RORIM.
|
|
#define SSI_MIS_RORMIS 0x00000001
|
|
#define SSI_MIS_RORMIS_BITN 0
|
|
#define SSI_MIS_RORMIS_M 0x00000001
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|
#define SSI_MIS_RORMIS_S 0
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Register: SSI_O_ICR
|
|
//
|
|
//*****************************************************************************
|
|
// Field: [1] RTIC
|
|
//
|
|
// Clear the receive timeout interrupt:
|
|
// Writing 1 to this field clears the timeout interrupt (RIS.RTRIS). Writing 0
|
|
// has no effect.
|
|
#define SSI_ICR_RTIC 0x00000002
|
|
#define SSI_ICR_RTIC_BITN 1
|
|
#define SSI_ICR_RTIC_M 0x00000002
|
|
#define SSI_ICR_RTIC_S 1
|
|
|
|
// Field: [0] RORIC
|
|
//
|
|
// Clear the receive overrun interrupt:
|
|
// Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS).
|
|
// Writing 0 has no effect.
|
|
#define SSI_ICR_RORIC 0x00000001
|
|
#define SSI_ICR_RORIC_BITN 0
|
|
#define SSI_ICR_RORIC_M 0x00000001
|
|
#define SSI_ICR_RORIC_S 0
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Register: SSI_O_DMACR
|
|
//
|
|
//*****************************************************************************
|
|
// Field: [1] TXDMAE
|
|
//
|
|
// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is
|
|
// enabled.
|
|
#define SSI_DMACR_TXDMAE 0x00000002
|
|
#define SSI_DMACR_TXDMAE_BITN 1
|
|
#define SSI_DMACR_TXDMAE_M 0x00000002
|
|
#define SSI_DMACR_TXDMAE_S 1
|
|
|
|
// Field: [0] RXDMAE
|
|
//
|
|
// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is
|
|
// enabled.
|
|
#define SSI_DMACR_RXDMAE 0x00000001
|
|
#define SSI_DMACR_RXDMAE_BITN 0
|
|
#define SSI_DMACR_RXDMAE_M 0x00000001
|
|
#define SSI_DMACR_RXDMAE_S 0
|
|
|
|
|
|
#endif // __SSI__
|