1
0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00
RIOT/boards/common/stm32/include/cfg_i2c1_pb6_pb7.h
Alexandre Abadie df18dba378
boards/stm32: introduce shared i2c configuration
This configuration corresponds to I2C1 connected to PB6 (SCL) and PB7 (SDA)
2019-09-02 08:17:21 +02:00

70 lines
1.5 KiB
C

/*
* Copyright (C) 2019 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Common configuration for STM32 I2C
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef CFG_I2C1_PB6_PB7_H
#define CFG_I2C1_PB6_PB7_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name I2C configuration
* @{
*/
static const i2c_conf_t i2c_config[] = {
{
.dev = I2C1,
.speed = I2C_SPEED_NORMAL,
.scl_pin = GPIO_PIN(PORT_B, 6),
.sda_pin = GPIO_PIN(PORT_B, 7),
#if CPU_FAM_STM32L4
.scl_af = GPIO_AF4,
.sda_af = GPIO_AF4,
#else /* CPU_FAM_STM32L0 */
.scl_af = GPIO_AF1,
.sda_af = GPIO_AF1,
#endif
.bus = APB1,
#if CPU_FAM_STM32L4
.rcc_mask = RCC_APB1ENR1_I2C1EN,
.irqn = I2C1_ER_IRQn,
#else /* CPU_FAM_STM32L0 */
.rcc_mask = RCC_APB1ENR_I2C1EN,
.irqn = I2C1_IRQn
#endif
}
};
#if CPU_FAM_STM32L4
#define I2C_0_ISR isr_i2c1_er
#else /* CPU_FAM_STM32L0 */
#define I2C_0_ISR isr_i2c1
#endif
#define I2C_NUMOF ARRAY_SIZE(i2c_config)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CFG_I2C1_PB6_PB7_H */
/** @} */