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146 lines
4.9 KiB
C
146 lines
4.9 KiB
C
/*
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* Copyright (C) 2015 TriaGnoSys GmbH
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* 2017 Alexander Kurth, Sören Tempel, Tristan Bruns
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* 2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Default clock configuration for STM32F0/F1/F3
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*
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* @author Víctor Ariño <victor.arino@triagnosys.com>
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* @author Sören Tempel <tempel@uni-bremen.de>
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* @author Tristan Bruns <tbruns@uni-bremen.de>
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* @author Alexander Kurth <kurth1@uni-bremen.de>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*
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*/
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#ifndef CLK_F0F1F3_CFG_CLOCK_DEFAULT_H
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#define CLK_F0F1F3_CFG_CLOCK_DEFAULT_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name F0/F1/F3 clock settings
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* @{
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*/
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE < MHZ(4) || CONFIG_CLOCK_HSE > MHZ(32))
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#error "HSE clock frequency must be between 4MHz and 32MHz"
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#endif
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/* The following parameters configure:
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- on F0: a 48MHz system clock with HSI (or default HSE) as input clock
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On stm32f031x6 and stm32f042x6 lines, there's no HSE and PREDIV is
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hard-wired to 2, so to reach 48MHz set PLL_PREDIV to 2 and PLL_MUL to 12 so
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system clock = (HSI8 / 2) * 12 = 48MHz
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- on F1/F3: a 72MHz system clock with HSE (8MHz or 16MHz) and HSI (8MHz) as input clock
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On stm32f303x6, stm32f303x8, stm32f303xB, stm32f303xC, stm32f328x8 and
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stm32f358xC lines, PREDIV is hard-wired to 2 (see RM0316 p.126 to p.128).
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To reach the maximum possible system clock (64MHz) set PLL_PREDIV to 2 and
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PLL_MUL to 16, so system clock = (HSI8 / 2) * 16 = 64MHz
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*/
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#ifndef CONFIG_CLOCK_PLL_PREDIV
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#if (IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(16))) || \
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defined(CPU_LINE_STM32F303x6) || defined(CPU_LINE_STM32F303x8) || \
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defined(CPU_LINE_STM32F303xB) || defined(CPU_LINE_STM32F303xC) || \
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defined(CPU_LINE_STM32F328x8) || defined(CPU_LINE_STM32F358xC) || \
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defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6)
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#define CONFIG_CLOCK_PLL_PREDIV (2)
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#else
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#define CONFIG_CLOCK_PLL_PREDIV (1)
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_MUL
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#ifdef CPU_FAM_STM32F0
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#if defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6)
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#define CONFIG_CLOCK_PLL_MUL (12)
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#else
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#define CONFIG_CLOCK_PLL_MUL (6)
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#endif
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#else /* CPU_FAM_F1 || CPU_FAM_F3 */
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#if defined(CPU_LINE_STM32F303x6) || defined(CPU_LINE_STM32F303x8) || \
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defined(CPU_LINE_STM32F303xB) || defined(CPU_LINE_STM32F303xC) || \
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defined(CPU_LINE_STM32F328x8) || defined(CPU_LINE_STM32F358xC)
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#define CONFIG_CLOCK_PLL_MUL (16)
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#else
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#define CONFIG_CLOCK_PLL_MUL (9)
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#endif
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#endif /* CPU_FAM_STM32F0 */
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#endif /* CONFIG_CLOCK_PLL_MUL */
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
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#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI)
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#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
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#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
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#error "The board doesn't provide an HSE oscillator"
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#endif
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#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE)
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#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
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#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE)
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#else /* CONFIG_CLOCK_HSI */
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#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI)
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#endif
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/* PLL configuration: make sure your values are legit!
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*
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* compute by: CORECLOCK = ((PLL_IN / PLL_PREDIV) * PLL_MUL)
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* with:
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* PLL_IN: input clock is HSE if available or HSI otherwise
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* PLL_PREDIV : pre-divider, allowed range: [1:16]
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* PLL_MUL: multiplier, allowed range: [2:16]
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* CORECLOCK -> 48MHz Max on F0, 72MHz MAX on F1/F3!
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*/
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#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_PREDIV) * CONFIG_CLOCK_PLL_MUL)
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#ifdef CPU_FAM_STM32F0
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#if CLOCK_CORECLOCK > MHZ(48)
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#error "SYSCLK cannot exceed 48MHz"
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#endif
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#else
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#if CLOCK_CORECLOCK > MHZ(72)
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#error "SYSCLK cannot exceed 72MHz"
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#endif
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#endif
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#endif /* CONFIG_USE_CLOCK_PLL */
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#define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 48MHz (F0), 72MHz (F1/F3)*/
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#ifndef CONFIG_CLOCK_APB1_DIV
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#ifdef CPU_FAM_STM32F0
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#define CONFIG_CLOCK_APB1_DIV (1)
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#else
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#define CONFIG_CLOCK_APB1_DIV (2)
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#endif
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#endif
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#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 48MHz (F0), 36MHz (F1/F3)*/
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#ifdef CPU_FAM_STM32F0
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/* APB2 and APB1 are the same bus but configuration registers still follows the
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* split between APB1 and APB2. Since it's the same bus, APB2 clock is equal to APB1 clock.
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*/
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#define CLOCK_APB2 (CLOCK_APB1)
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#else
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#ifndef CONFIG_CLOCK_APB2_DIV
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#define CONFIG_CLOCK_APB2_DIV (1)
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#endif
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#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK2, max: 72MHz */
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#endif
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CLK_F0F1F3_CFG_CLOCK_DEFAULT_H */
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/** @} */
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