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https://github.com/RIOT-OS/RIOT.git
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140 lines
2.6 KiB
C
140 lines
2.6 KiB
C
/*
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* Copyright (C) 2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_nrf52
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* @{
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*
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* @file
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* @brief Shared IRQ handling between SPI and TWI peripherals on the nRF52
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* devices
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*
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* I2C is called TWI (Two Wire Interface) in the datasheets from Nordic
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*
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* @author Koen Zandberg <koen@bergzand.net>
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*
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* @}
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*/
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#include "cpu.h"
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#include "periph_cpu.h"
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/* nRF52811 ISR names */
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#if defined(CPU_MODEL_NRF52811XXAA)
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#define ISR_SPIM0 isr_spi0
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#define ISR_SPIM1 isr_spi1_twi0
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/* nRF52832 and nRF52840 ISR names */
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#elif (defined(CPU_MODEL_NRF52840XXAA) || defined(CPU_MODEL_NRF52832XXAA))
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#define ISR_SPIM0 isr_spi0_twi0
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#define ISR_SPIM1 isr_spi1_twi1
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#else
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#error Unknown nrf52 MCU model
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#endif
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static spi_twi_irq_cb_t _irq[SPIM_COUNT];
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static void *_irq_arg[SPIM_COUNT];
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/* I2C and SPI share peripheral addresses */
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static size_t _spi_dev2num(void *dev)
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{
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if (dev == NRF_SPIM0) {
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return 0;
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}
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else if (dev == NRF_SPIM1) {
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return 1;
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}
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#ifdef NRF_SPIM2
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else if (dev == NRF_SPIM2) {
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return 2;
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}
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#endif /* NRF_SPIM2 */
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#ifdef NRF_SPIM3
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else if (dev == NRF_SPIM3) {
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return 3;
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}
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#endif /* NRF_SPIM3 */
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else {
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assert(false);
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return 0;
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}
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}
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static inline size_t _i2c_dev2num(void *dev)
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{
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return _spi_dev2num(dev);
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}
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static const IRQn_Type _isr[] = {
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SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn,
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#ifdef CPU_MODEL_NRF52811XXAA
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TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQn,
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#else
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SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn,
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#endif
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#ifdef NRF_SPIM2
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SPIM2_SPIS2_SPI2_IRQn,
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#endif
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#ifdef NRF_SPIM3
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SPIM3_IRQn,
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#endif /* CPU_MODEL_NRF52840XXAA */
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};
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void spi_twi_irq_register_spi(NRF_SPIM_Type *bus,
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spi_twi_irq_cb_t cb, void *arg)
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{
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size_t num = _spi_dev2num(bus);
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_irq[num] = cb;
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_irq_arg[num] = arg;
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NVIC_EnableIRQ(_isr[num]);
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}
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void spi_twi_irq_register_i2c(NRF_TWIM_Type *bus,
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spi_twi_irq_cb_t cb, void *arg)
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{
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size_t num = _i2c_dev2num(bus);
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_irq[num] = cb;
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_irq_arg[num] = arg;
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NVIC_EnableIRQ(_isr[num]);
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}
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void ISR_SPIM0(void)
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{
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_irq[0](_irq_arg[0]);
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cortexm_isr_end();
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}
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void ISR_SPIM1(void)
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{
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_irq[1](_irq_arg[1]);
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cortexm_isr_end();
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}
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#ifdef NRF_SPIM2
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void isr_spi2(void)
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{
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_irq[2](_irq_arg[2]);
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cortexm_isr_end();
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}
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#endif
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#ifdef NRF_SPIM3
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void isr_spi3(void)
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{
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_irq[3](_irq_arg[3]);
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cortexm_isr_end();
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}
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#endif /* NRF_SPIM3 */
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