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https://github.com/RIOT-OS/RIOT.git
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307e8c7a17
Introduce XMEGA EBI driver. This enable EBI for use with all memory supported by the device and peripherals. It include support to SRAM, SDRAM, LCDs or any other external bus access. Note: This feature only works for A1/A1U series, which are, the series with EBI hardware. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
153 lines
3.7 KiB
C
153 lines
3.7 KiB
C
/*
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* Copyright (C) 2021 Gerson Fernando Budke
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_atxmega-a1u-xpro
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the ATxmegaA1U Xplained Pro board.
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*
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* @author Gerson Fernando Budke <nandojve@gmail.com>
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*/
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#include "mutex.h"
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <avr/io.h>
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#include "periph_cpu.h"
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/**
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* @name Timer peripheral configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = (void *)&TCC1,
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.pwr = PWR_RED_REG(PWR_PORT_C, PR_TC1_bm),
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.type = TC_TYPE_1,
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.int_lvl = { CPU_INT_LVL_LOW,
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CPU_INT_LVL_OFF,
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CPU_INT_LVL_OFF,
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CPU_INT_LVL_OFF },
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},
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{
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.dev = (void *)&TCC0,
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.pwr = PWR_RED_REG(PWR_PORT_C, PR_TC0_bm),
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.type = TC_TYPE_0,
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.int_lvl = { CPU_INT_LVL_LOW,
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CPU_INT_LVL_LOW,
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CPU_INT_LVL_LOW,
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CPU_INT_LVL_LOW },
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}
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};
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#define TIMER_0_ISRA TCC1_CCA_vect
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#define TIMER_1_ISRA TCC0_CCA_vect
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#define TIMER_1_ISRB TCC0_CCB_vect
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#define TIMER_1_ISRC TCC0_CCC_vect
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#define TIMER_1_ISRD TCC0_CCD_vect
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{ /* CDC-ACM */
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.dev = &USARTE0,
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.pwr = PWR_RED_REG(PWR_PORT_E, PR_USART0_bm),
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.rx_pin = GPIO_PIN(PORT_E, 2),
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.tx_pin = GPIO_PIN(PORT_E, 3),
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#ifdef MODULE_PERIPH_UART_HW_FC
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.rts_pin = GPIO_UNDEF,
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.cts_pin = GPIO_UNDEF,
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#endif
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.rx_int_lvl = CPU_INT_LVL_LOW,
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.tx_int_lvl = CPU_INT_LVL_LOW,
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.dre_int_lvl = CPU_INT_LVL_OFF,
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},
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};
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/* interrupt function name mapping */
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#define UART_0_RXC_ISR USARTE0_RXC_vect /* Reception Complete Interrupt */
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#define UART_0_DRE_ISR USARTE0_DRE_vect /* Data Register Empty Interrupt */
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#define UART_0_TXC_ISR USARTE0_TXC_vect /* Transmission Complete Interrupt */
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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static const i2c_conf_t i2c_config[] = {
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{
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.dev = &TWIC,
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.pwr = PWR_RED_REG(PWR_PORT_C, PR_TWI_bm),
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.sda_pin = GPIO_PIN(PORT_C, 0),
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.scl_pin = GPIO_PIN(PORT_C, 1),
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.speed = I2C_SPEED_NORMAL,
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.int_lvl = CPU_INT_LVL_LOW,
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},
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};
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#define I2C_0_ISR TWIC_TWIM_vect
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#define I2C_NUMOF ARRAY_SIZE(i2c_config)
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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static const spi_conf_t spi_config[] = {
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{
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.dev = &SPIC,
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.pwr = PWR_RED_REG(PWR_PORT_C, PR_SPI_bm),
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.sck_pin = GPIO_PIN(PORT_C, 7),
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.miso_pin = GPIO_PIN(PORT_C, 6),
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.mosi_pin = GPIO_PIN(PORT_C, 5),
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.ss_pin = GPIO_PIN(PORT_C, 4),
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},
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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/**
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* @name EBI configuration
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*
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* For more information, see ebi_conf_t structure.
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*
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* @{
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*/
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static const ebi_conf_t ebi_config = {
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0
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};
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#include "periph_conf_common.h"
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#endif /* PERIPH_CONF_H */
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/** @} */
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