mirror of
https://github.com/RIOT-OS/RIOT.git
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126 lines
4.1 KiB
C
126 lines
4.1 KiB
C
/*
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* Copyright (C) 2015 Engineering-Spirit
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32f2
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* @{
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*
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* @file
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* @brief Implementation of the kernel cpu functions
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*
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* @author Nick v. IJzendoorn <nijzendoorn@engineering-spirit.nl>
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* @}
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*/
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#include "cpu.h"
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#include "periph_conf.h"
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#include "periph/init.h"
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#ifdef HSI_VALUE
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# define RCC_CR_SOURCE RCC_CR_HSION
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# define RCC_CR_SOURCE_RDY RCC_CR_HSIRDY
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# define RCC_PLL_SOURCE RCC_PLLCFGR_PLLSRC_HSI
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#else
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# define RCC_CR_SOURCE RCC_CR_HSEON
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# define RCC_CR_SOURCE_RDY RCC_CR_HSERDY
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# define RCC_PLL_SOURCE RCC_PLLCFGR_PLLSRC_HSE
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#endif
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static void clk_init(void);
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void cpu_init(void)
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{
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/* initialize the Cortex-M core */
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cortexm_init();
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/* initialize system clocks */
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clk_init();
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/* trigger static peripheral initialization */
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periph_init();
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}
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/**
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* @brief Configure the clock system of the stm32f2
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*
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*/
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static void clk_init(void)
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{
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/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
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/* Set HSION bit */
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RCC->CR |= 0x00000001U;
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/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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RCC->CFGR = 0x00000000U;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= 0xFEF6FFFFU;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x24003010U;
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/* Reset HSEBYP bit */
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RCC->CR &= 0xFFFBFFFFU;
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/* Disable all interrupts and clear pending bits */
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RCC->CIR = 0x00000000U;
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/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration */
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/* Enable the high speed clock source */
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RCC->CR |= RCC_CR_SOURCE;
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/* Wait till hish speed clock source is ready,
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* NOTE: the MCU will stay here forever if no HSE clock is connected */
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while ((RCC->CR & RCC_CR_SOURCE_RDY) == 0);
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/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
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FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN;
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/* Flash 2 wait state */
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FLASH->ACR &= ~((uint32_t)FLASH_ACR_LATENCY);
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FLASH->ACR |= (uint32_t)CLOCK_FLASH_LATENCY;
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/* HCLK = SYSCLK */
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RCC->CFGR |= (uint32_t)CLOCK_AHB_DIV;
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/* PCLK2 = HCLK */
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RCC->CFGR |= (uint32_t)CLOCK_APB2_DIV;
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/* PCLK1 = HCLK */
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RCC->CFGR |= (uint32_t)CLOCK_APB1_DIV;
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/* reset PLL config register */
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RCC->PLLCFGR &= ~((uint32_t)(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLQ));
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/* set HSE as source for the PLL */
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RCC->PLLCFGR |= RCC_PLL_SOURCE;
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/* set division factor for main PLL input clock */
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RCC->PLLCFGR |= (CLOCK_PLL_M & 0x3F);
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/* set main PLL multiplication factor for VCO */
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RCC->PLLCFGR |= (CLOCK_PLL_N & 0x1FF) << 6;
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/* set main PLL division factor for main system clock */
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RCC->PLLCFGR |= (((CLOCK_PLL_P & 0x03) >> 1) - 1) << 16;
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/* set main PLL division factor for USB OTG FS, SDIO and RNG clocks */
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RCC->PLLCFGR |= (CLOCK_PLL_Q & 0x0F) << 24;
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#ifdef ENABLE_PLLI2S_MCO2
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/* reset PLL I2S config register */
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RCC->PLLI2SCFGR = 0x00000000U;
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/* set PLL I2S division factor */
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RCC->PLLI2SCFGR |= (CLOCK_PLL_I2S_R & 0x07) << 28;
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/* set PLL I2S multiplication factor */
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RCC->PLLI2SCFGR |= (CLOCK_PLL_I2S_N & 0x1FF) << 6;
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/* MCO2 output is PLLI2S */
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RCC->CFGR |= (uint32_t) RCC_CFGR_MCO2_0;
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RCC->CFGR &= ~(uint32_t) RCC_CFGR_MCO2_1;
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/* MCO2 prescaler div by 5 */
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RCC->CFGR |= (uint32_t) ((CLOCK_MC02_PRE + 4 - 2) & 0x7) << 27;
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/* enable PLL I2S clock */
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RCC->CR |= RCC_CR_PLLI2SON;
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/* wait till PLL I2S clock is ready */
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while ((RCC->CR & RCC_CR_PLLI2SRDY) == 0) {}
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#endif
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/* Enable PLL */
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RCC->CR |= RCC_CR_PLLON;
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/* Wait till PLL is ready */
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while ((RCC->CR & RCC_CR_PLLRDY) == 0);
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/* Select PLL as system clock source */
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RCC->CFGR &= ~((uint32_t)(RCC_CFGR_SW));
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RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
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}
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