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c7e334d3dc
According to the STM32F3 clocktree (ref. manual p. 126) the I2CX hardware is driven by either HSI or SYSCLK. If HSI is deactivated SYSCLK clock must be selected as I2CX clock. Signed-off-by: Steffen Pengel <steffen.pengel@gmail.com>
155 lines
4.5 KiB
C
155 lines
4.5 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32f3
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* @{
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*
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* @file
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* @brief Implementation of the CPU initialization
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl>
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* @}
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*/
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#include <stdint.h>
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#include "cpu.h"
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#include "periph_conf.h"
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#include "periph/init.h"
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/* Check the source to be used for the PLL */
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#if defined(CLOCK_HSI) && defined(CLOCK_HSE)
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#error "Only provide one of two CLOCK_HSI/CLOCK_HSE"
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#elif CLOCK_HSI
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#define CLOCK_CR_SOURCE RCC_CR_HSION
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#define CLOCK_CR_SOURCE_RDY RCC_CR_HSIRDY
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#ifdef RCC_CFGR_PLLSRC_HSI_DIV2
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#define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSI_DIV2)
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#define CLOCK_PLL_MUL_MULTIPLIER 2
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#else
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#define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSI_PREDIV)
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#define CLOCK_PLL_MUL_MULTIPLIER 1
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#endif
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#define CLOCK_DISABLE_HSI 0
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#elif CLOCK_HSE
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#define CLOCK_CR_SOURCE RCC_CR_HSEON
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#define CLOCK_CR_SOURCE_RDY RCC_CR_HSERDY
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#define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1)
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#define CLOCK_PLL_MUL_MULTIPLIER 1
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#define CLOCK_DISABLE_HSI 1
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#else
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#error "Please provide CLOCK_HSI or CLOCK_HSE in boards/NAME/includes/perhip_cpu.h"
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#endif
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static void cpu_clock_init(void);
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/**
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* @brief Initialize the CPU, set IRQ priorities
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*/
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void cpu_init(void)
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{
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/* initialize the Cortex-M core */
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cortexm_init();
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/* initialize the clock system */
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cpu_clock_init();
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/* trigger static peripheral initialization */
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periph_init();
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}
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/**
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* @brief Configure the controllers clock system
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*
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* The clock initialization make the following assumptions:
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* - the HSI and HSE selection is based on the CLOCK_HSI or CLOCK_HSE define in the periph_conf.h
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* - the internal PLL circuit is used for clock refinement
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*
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* The actual used values are specified in the board's `periph_conf.h` file.
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*
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* NOTE: currently there is not timeout for initialization of PLL and other locks
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* -> when wrong values are chosen, the initialization could stall
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*/
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static void cpu_clock_init(void)
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{
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/* configure the high speed clock */
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/* reset clock configuration register */
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RCC->CFGR = 0;
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/* disable HSE, CSS and PLL */
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RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON);
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/* disable all clock interrupts */
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RCC->CIR = 0;
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/* enable the high speed clock */
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RCC->CR |= CLOCK_CR_SOURCE;
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/* wait for high speed clock to be ready */
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while (!(RCC->CR & CLOCK_CR_SOURCE_RDY)) {}
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/* setup the peripheral bus prescalers */
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/* set the AHB clock divider */
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RCC->CFGR &= ~RCC_CFGR_HPRE;
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RCC->CFGR |= CLOCK_AHB_DIV;
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/* set the APB2 (high speed) bus clock divider */
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RCC->CFGR &= ~RCC_CFGR_PPRE2;
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RCC->CFGR |= CLOCK_APB2_DIV;
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/* set the APB1 (low speed) bus clock divider */
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RCC->CFGR &= ~RCC_CFGR_PPRE1;
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RCC->CFGR |= CLOCK_APB1_DIV;
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/* configure the PLL */
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/* reset PLL configuration */
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RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL);
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/* set PLL to use high speed clock with prescaler 1 as input */
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RCC->CFGR |= CLOCK_PLL_SOURCE | ((((CLOCK_PLL_MUL * CLOCK_PLL_MUL_MULTIPLIER) - 2) & 0xf) << 18);
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/* enable PLL again */
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RCC->CR |= RCC_CR_PLLON;
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/* wait until PLL is stable */
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while(!(RCC->CR & RCC_CR_PLLRDY)) {}
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/* configure flash latency */
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/* reset flash access control register */
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FLASH->ACR = 0;
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/* enable pre-fetch buffer */
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FLASH->ACR |= FLASH_ACR_PRFTBE;
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/* set flash latency */
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FLASH->ACR &= ~FLASH_ACR_LATENCY;
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FLASH->ACR |= CLOCK_FLASH_LATENCY;
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/* configure the sysclock and the peripheral clocks */
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/* set sysclock to be driven by the PLL clock */
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RCC->CFGR &= ~RCC_CFGR_SW;
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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/* wait for sysclock to be stable */
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while (!(RCC->CFGR & RCC_CFGR_SWS_PLL)) {}
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#if CLOCK_DISABLE_HSI
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/* disable the HSI if we use the HSE */
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RCC->CR &= ~(RCC_CR_HSION);
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while (RCC->CR & RCC_CR_HSIRDY) {}
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/* swith I2Cx clock source to SYSCLK */
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RCC->CFGR3 &= ~(RCC_CFGR3_I2CSW);
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RCC->CFGR3 |= RCC_CFGR3_I2C1SW_SYSCLK;
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#ifdef RCC_CFGR3_I2C2SW_SYSCLK
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RCC->CFGR3 |= RCC_CFGR3_I2C2SW_SYSCLK;
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#endif
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#ifdef RCC_CFGR3_I2C3SW_SYSCLK
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RCC->CFGR3 |= RCC_CFGR3_I2C3SW_SYSCLK;
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#endif
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#endif
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}
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