mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
1d0f90dcdf
- Fixed documentation
- Use bitwise operation instead of multiplication and addition in `GPIO_PIN()`
- Allow GPIOs to be configured as input via `gpio_init()`
- Fixed bugs in `gpio_init_mux`:
- `0x01 << ((pin & 31) * 2)` was used before to generate the bitmask, but
this would shift by 62 to the left. Correct is `0x01 << ((pin & 15) * 2)`
(See [datasheet](https://www.nxp.com/docs/en/user-guide/UM10211.pdf) at
pages 156ff)
- Only one of the two bits was cleared previously
- Changed strategy to access GPIO pins:
- Previous strategy:
- Set all bits in FIOMASK except the one for the pin to control to
disable access to them
- Set/clear/read all pins in the target GPIO port (but access to all but
the target pin is ignored because of the applied FIOMASK)
- New strategy:
- Set/clear/read only the target pin
- Advantages:
- Only one access to a GPIO register instead of two
- Proven approach: Access to GPIOs on lpc2387 is mostly done by
accessing the GPIO registers directy (e.g. see the sht11 driver).
Those accesses never touch the FIOMASK register
- No unwanted side effects: Disabling all but one pin in a GPIO port
without undoing that seems not to be a good idea
114 lines
2.9 KiB
C
114 lines
2.9 KiB
C
/*
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* Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_lpc2387
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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*/
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#ifndef PERIPH_CPU_H
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#define PERIPH_CPU_H
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#include "cpu.h"
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#include "periph/dev_enums.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include "cpu.h"
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/**
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* @brief LPC2387 MCU defines
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* @{
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*/
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#define __IO volatile
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/**
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* @brief Fast GPIO register definition struct
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*/
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typedef struct {
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/** @brief Direction: Output if corresponding bit is set, otherwise input */
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__IO uint32_t DIR;
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/** @brief 12 bytes of reseved memory we don't need to access */
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uint32_t _reserved[3];
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/** @brief Set bits to ignore corresponding bits when accessing `PIN`, `SET`
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* or `CLR` register of this port
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*/
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__IO uint32_t MASK;
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/** @brief The current state of each pin of this port is accessible here
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* (regardless of direction): If bit is set input is high
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*/
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__IO uint32_t PIN;
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/** @brief Output pins are set to high by setting the corresponding bit */
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__IO uint32_t SET;
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/** @brief Output pins are set to low by setting the corresponding bit */
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__IO uint32_t CLR;
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} FIO_PORT_t;
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#define FIO_PORTS ((FIO_PORT_t*)FIO_BASE_ADDR)
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#define PINSEL ((__IO uint32_t *)(PINSEL_BASE_ADDR))
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#define PINMODE ((__IO uint32_t *)(PINSEL_BASE_ADDR + 0x40))
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int gpio_init_mux(unsigned pin, unsigned mux);
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void gpio_init_states(void);
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#define GPIO_PIN(port, pin) (port<<5 | pin)
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#ifndef DOXYGEN
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#define HAVE_GPIO_FLANK_T
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typedef enum {
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GPIO_FALLING = 1, /**< emit interrupt on falling flank */
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GPIO_RISING = 2, /**< emit interrupt on rising flank */
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GPIO_BOTH = 3 /**< emit interrupt on both flanks */
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} gpio_flank_t;
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#endif /* ndef DOXYGEN */
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/**
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* @brief Number of available timer channels
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*/
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#define TIMER_CHAN_NUMOF (4U)
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/**
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* @brief Declare needed generic SPI functions
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* @{
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*/
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#define PERIPH_SPI_NEEDS_INIT_CS
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#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
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#define PERIPH_SPI_NEEDS_TRANSFER_REG
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#define PERIPH_SPI_NEEDS_TRANSFER_REGS
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/* @} */
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/**
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* @brief Override SPI clock speed values
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* @{
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*/
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#define HAVE_SPI_CLK_T
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typedef enum {
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SPI_CLK_100KHZ = 100, /**< drive the SPI bus with 100KHz */
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SPI_CLK_400KHZ = 400, /**< drive the SPI bus with 400KHz */
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SPI_CLK_1MHZ = 1000, /**< drive the SPI bus with 1MHz */
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SPI_CLK_5MHZ = 5000, /**< drive the SPI bus with 5MHz */
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SPI_CLK_10MHZ = 10000 /**< drive the SPI bus with 10MHz */
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} spi_clk_t;
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/** @} */
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/* @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_H */
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/** @} */
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