mirror of
https://github.com/RIOT-OS/RIOT.git
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195 lines
6.1 KiB
C
195 lines
6.1 KiB
C
/* Copyright (C) 2004, 2005, 2006 Board of Trustees, Leland Stanford
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* Jr. University. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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// Copy of Pintos' threads/io.h, license header extracted from Pintos' LICENSE file.
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#ifndef CPU__X86__PORTS_H__
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#define CPU__X86__PORTS_H__
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#include <stdlib.h>
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Reads and returns a byte from PORT.
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* @param[in] port Port to read from.
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* @returns Read value.
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*/
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static inline uint8_t __attribute__((always_inline)) inb(uint16_t port)
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{
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/* See [IA32-v2a] "IN". */
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uint8_t data;
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__asm__ volatile("inb %w1, %b0" : "=a"(data) : "Nd"(port));
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return data;
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}
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/**
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* @brief Reads multiple bytes from a port.
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* @param[in] port Port to read from.
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* @param[out] addr Buffer to write the read values into.
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* @param[in] cnt Number of bytes to read.
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*/
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static inline void __attribute__((always_inline)) insb(uint16_t port, void *addr, size_t cnt)
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{
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/* See [IA32-v2a] "INS". */
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__asm__ volatile("rep insb" : "+D"(addr), "+c"(cnt) : "d"(port) : "memory");
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}
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/**
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* @brief Reads and returns a word from PORT.
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* @param[in] port Port to read from.
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* @returns Read value.
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*/
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static inline uint16_t __attribute__((always_inline)) inw(uint16_t port)
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{
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uint16_t data;
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/* See [IA32-v2a] "IN". */
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__asm__ volatile("inw %w1, %w0" : "=a"(data) : "Nd"(port));
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return data;
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}
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/**
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* @brief Reads multiple words from a port.
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* @param[in] port Port to read from.
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* @param[out] addr Buffer to write the read values into.
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* @param[in] cnt Number of words to read.
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*/
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static inline void __attribute__((always_inline)) insw(uint16_t port, void *addr, size_t cnt)
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{
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/* See [IA32-v2a] "INS". */
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__asm__ volatile("rep insw" : "+D"(addr), "+c"(cnt) : "d"(port) : "memory");
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}
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/**
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* @brief Reads and returns a long from PORT.
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* @param[in] port Port to read from.
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* @returns Read value.
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*/
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static inline uint32_t __attribute__((always_inline)) inl(uint16_t port)
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{
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/* See [IA32-v2a] "IN". */
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uint32_t data;
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__asm__ volatile("inl %w1, %0" : "=a"(data) : "Nd"(port));
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return data;
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}
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/**
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* @brief Reads multiple longs from a port.
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* @param[in] port Port to read from.
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* @param[out] addr Buffer to write the read values into.
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* @param[in] cnt Number of words to read.
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*/
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static inline void __attribute__((always_inline)) insl(uint16_t port, void *addr, size_t cnt)
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{
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/* See [IA32-v2a] "INS". */
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__asm__ volatile("rep insl" : "+D"(addr), "+c"(cnt) : "d"(port) : "memory");
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}
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/**
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* @brief Writes a byte into a port.
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* @param[in] port Port to write into.
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* @param[in] data Byte to write.
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*/
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static inline void __attribute__((always_inline)) outb(uint16_t port, uint8_t data)
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{
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/* See [IA32-v2b] "OUT". */
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__asm__ volatile("outb %b0, %w1" : : "a"(data), "Nd"(port));
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}
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/**
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* @brief Writes multiple bytes into a port.
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* @param[in] port Port to write into.
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* @param[in] addr Buffer to read from.
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* @param[in] cnt Number of bytes to write.
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*/
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static inline void __attribute__((always_inline)) outsb(uint16_t port, const void *addr, size_t cnt)
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{
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/* See [IA32-v2b] "OUTS". */
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__asm__ volatile("rep outsb" : "+S"(addr), "+c"(cnt) : "d"(port));
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}
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/**
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* @brief Writes a word into a port.
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* @param[in] port Port to write into.
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* @param[in] data Word to write.
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*/
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static inline void __attribute__((always_inline)) outw(uint16_t port, uint16_t data)
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{
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/* See [IA32-v2b] "OUT". */
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__asm__ volatile("outw %w0, %w1" : : "a"(data), "Nd"(port));
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}
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/**
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* @brief Writes multiple words into a port.
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* @param[in] port Port to write into.
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* @param[in] addr Buffer to read from.
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* @param[in] cnt Number of words to write.
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*/
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static inline void __attribute__((always_inline)) outsw(uint16_t port, const void *addr, size_t cnt)
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{
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/* See [IA32-v2b] "OUTS". */
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__asm__ volatile("rep outsw" : "+S"(addr), "+c"(cnt) : "d"(port));
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}
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/**
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* @brief Writes a long into a port.
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* @param[in] port Port to write into.
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* @param[in] data Long to write.
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*/
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static inline void __attribute__((always_inline)) outl(uint16_t port, uint32_t data)
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{
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/* See [IA32-v2b] "OUT". */
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__asm__ volatile("outl %0, %w1" : : "a"(data), "Nd"(port));
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}
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/**
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* @brief Writes multiple longs into a port.
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* @param[in] port Port to write into.
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* @param[in] addr Buffer to read from.
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* @param[in] cnt Number of longs to write.
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*/
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static inline void __attribute__((always_inline)) outsl(uint16_t port, const void *addr, size_t cnt)
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{
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/* See [IA32-v2b] "OUTS". */
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__asm__ volatile("rep outsl" : "+S"(addr), "+c"(cnt) : "d"(port));
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}
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/**
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* @brief Make sure a write to a port was already acknowledged.
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*/
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static inline void __attribute__((always_inline)) io_wait(void)
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{
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__asm__ volatile(" jmp 1f\n"
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"1: jmp 2f\n"
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"2:");
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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