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140 lines
3.0 KiB
C
140 lines
3.0 KiB
C
/*
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* Copyright (C) 2014-2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32f1
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* @{
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*
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* @file
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* @brief Low-level UART driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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*
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* @}
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*/
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#include <math.h>
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#include "cpu.h"
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#include "board.h"
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#include "periph_conf.h"
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#include "periph/uart.h"
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#include "periph/gpio.h"
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#include "sched.h"
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#include "thread.h"
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/**
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* @brief Allocate memory to store the callback functions.
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*/
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static uart_isr_ctx_t isr_ctx[UART_NUMOF];
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static inline USART_TypeDef *dev(uart_t uart)
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{
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return uart_config[uart].dev;
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}
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static void clk_en(uart_t uart)
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{
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if (uart_config[uart].bus == APB1) {
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RCC->APB1ENR |= uart_config[uart].rcc_pin;
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}
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else {
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RCC->APB2ENR |= uart_config[uart].rcc_pin;
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}
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}
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int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
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{
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uint32_t bus_clk;
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uint16_t mantissa;
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uint8_t fraction;
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/* make sure the given device is valid */
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if (uart >= UART_NUMOF) {
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return -1;
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}
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/* save ISR context */
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isr_ctx[uart].rx_cb = rx_cb;
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isr_ctx[uart].arg = arg;
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/* configure RX and TX pin */
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gpio_init(uart_config[uart].rx_pin, GPIO_IN);
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gpio_init_af(uart_config[uart].tx_pin, GPIO_AF_OUT_PP);
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/* enable the clock */
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clk_en(uart);
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/* reset UART configuration -> defaults to 8N1 mode */
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dev(uart)->CR1 = 0;
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dev(uart)->CR2 = 0;
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dev(uart)->CR3 = 0;
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/* calculate and apply baudrate */
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bus_clk = (uart_config[uart].bus == APB1) ? CLOCK_APB1 : CLOCK_APB2;
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bus_clk /= baudrate;
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mantissa = (uint16_t)(bus_clk / 16);
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fraction = (uint8_t)(bus_clk - (mantissa * 16));
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dev(uart)->BRR = ((mantissa & 0x0fff) << 4) | (fraction & 0x0f);
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/* enable the UART's global interrupt and activate it */
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NVIC_EnableIRQ(uart_config[uart].irqn);
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dev(uart)->CR1 = (USART_CR1_UE | USART_CR1_TE |
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USART_CR1_RE | USART_CR1_RXNEIE);
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return 0;
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}
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void uart_write(uart_t uart, const uint8_t *data, size_t len)
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{
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for (size_t i = 0; i < len; i++) {
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while(!(dev(uart)->SR & USART_SR_TXE)) {}
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dev(uart)->DR = data[i];
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}
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}
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static inline void irq_handler(uart_t uart)
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{
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uint32_t status = dev(uart)->SR;
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if (status & USART_SR_RXNE) {
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char data = (char)dev(uart)->DR;
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isr_ctx[uart].rx_cb(isr_ctx[uart].arg, data);
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}
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if (status & USART_SR_ORE) {
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/* ORE is cleared by reading SR and DR sequentially */
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dev(uart)->DR;
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}
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if (sched_context_switch_request) {
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thread_yield();
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}
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}
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#ifdef UART_0_ISR
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void UART_0_ISR(void)
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{
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irq_handler(0);
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}
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#endif
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#ifdef UART_1_ISR
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void UART_1_ISR(void)
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{
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irq_handler(1);
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}
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#endif
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#ifdef UART_2_ISR
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void UART_2_ISR(void)
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{
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irq_handler(2);
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}
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#endif
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