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eeb359e80c
The implmentation of `timer_set_absolute()` has The following problems. First, it attempts to restore the auto reload register (ARR) to it's default if the ARR was previosly set by `timer_set_periodic()` by comparing it to the channel's capture compare (CC) register _after_ it has already set the CC register. Secondly, it clears spurious IRQs _after_ the CC register has been set. If the value being set is equal to the timer's current count (or the two become equal before the supurios IRQ clearing happens), this could cause a legitimate IRQ to be cleared. The implmentation of `timer_set()` has the same error in handling the ARR as described above. This patch reorders the operations of both functions to do: 1. handle ARR 2. clear spurious IRQs 3. set channel's CC 4. enable IRQ Additionally, the calulation of `value` in `timer_set()` is moved earlier in the function's exec path as a pedantic measure.
330 lines
6.9 KiB
C
330 lines
6.9 KiB
C
/*
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* Copyright (C) 2014-2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32
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* @ingroup drivers_periph_timer
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* @{
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*
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* @file
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* @brief Low-level timer driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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*
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* @}
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*/
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#include "cpu.h"
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#include "periph/timer.h"
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/**
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* @brief Interrupt context for each configured timer
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*/
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static timer_isr_ctx_t isr_ctx[TIMER_NUMOF];
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/**
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* @brief Get the timer device
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*/
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static inline TIM_TypeDef *dev(tim_t tim)
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{
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return timer_config[tim].dev;
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}
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#ifdef MODULE_PERIPH_TIMER_PERIODIC
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/**
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* @brief Helper macro to get channel bit in timer/channel bitmap
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*/
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#define CHAN_BIT(tim, chan) (1 << chan) << (TIMER_CHANNEL_NUMOF * (tim & 1))
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/**
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* @brief Bitmap for compare channel disable after match
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*/
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static uint8_t _oneshot[(TIMER_NUMOF+1)/2];
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/**
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* @brief Clear interrupt enable after the interrupt has fired
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*/
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static inline void set_oneshot(tim_t tim, int chan)
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{
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_oneshot[tim >> 1] |= CHAN_BIT(tim, chan);
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}
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/**
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* @brief Enable interrupt with every wrap-around of the timer
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*/
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static inline void clear_oneshot(tim_t tim, int chan)
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{
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_oneshot[tim >> 1] &= ~CHAN_BIT(tim, chan);
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}
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static inline bool is_oneshot(tim_t tim, int chan)
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{
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return _oneshot[tim >> 1] & CHAN_BIT(tim, chan);
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}
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#else /* !MODULE_PERIPH_TIMER_PERIODIC */
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static inline void set_oneshot(tim_t tim, int chan)
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{
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(void)tim;
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(void)chan;
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}
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static inline bool is_oneshot(tim_t tim, int chan)
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{
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(void)tim;
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(void)chan;
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return true;
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}
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#endif /* MODULE_PERIPH_TIMER_PERIODIC */
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int timer_init(tim_t tim, uint32_t freq, timer_cb_t cb, void *arg)
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{
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/* check if device is valid */
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if (tim >= TIMER_NUMOF) {
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return -1;
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}
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/* remember the interrupt context */
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isr_ctx[tim].cb = cb;
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isr_ctx[tim].arg = arg;
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/* enable the peripheral clock */
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periph_clk_en(timer_config[tim].bus, timer_config[tim].rcc_mask);
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/* configure the timer as upcounter in continuous mode */
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dev(tim)->CR1 = 0;
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dev(tim)->CR2 = 0;
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dev(tim)->ARR = timer_config[tim].max;
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/* set prescaler */
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dev(tim)->PSC = ((periph_timer_clk(timer_config[tim].bus) / freq) - 1);
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/* generate an update event to apply our configuration */
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dev(tim)->EGR = TIM_EGR_UG;
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/* enable the timer's interrupt */
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NVIC_EnableIRQ(timer_config[tim].irqn);
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/* reset the counter and start the timer */
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timer_start(tim);
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return 0;
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}
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int timer_set_absolute(tim_t tim, int channel, unsigned int value)
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{
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if (channel >= (int)TIMER_CHANNEL_NUMOF) {
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return -1;
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}
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unsigned irqstate = irq_disable();
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set_oneshot(tim, channel);
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#ifdef MODULE_PERIPH_TIMER_PERIODIC
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if (dev(tim)->ARR == TIM_CHAN(tim, channel)) {
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dev(tim)->ARR = timer_config[tim].max;
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}
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#endif
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/* clear spurious IRQs */
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dev(tim)->SR &= ~(TIM_SR_CC1IF << channel);
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TIM_CHAN(tim, channel) = (value & timer_config[tim].max);
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/* enable IRQ */
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dev(tim)->DIER |= (TIM_DIER_CC1IE << channel);
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irq_restore(irqstate);
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return 0;
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}
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int timer_set(tim_t tim, int channel, unsigned int timeout)
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{
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unsigned value = (dev(tim)->CNT + timeout) & timer_config[tim].max;
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if (channel >= (int)TIMER_CHANNEL_NUMOF) {
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return -1;
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}
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unsigned irqstate = irq_disable();
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set_oneshot(tim, channel);
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#ifdef MODULE_PERIPH_TIMER_PERIODIC
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if (dev(tim)->ARR == TIM_CHAN(tim, channel)) {
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dev(tim)->ARR = timer_config[tim].max;
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}
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#endif
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/* clear spurious IRQs */
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dev(tim)->SR &= ~(TIM_SR_CC1IF << channel);
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TIM_CHAN(tim, channel) = value;
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/* enable IRQ */
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dev(tim)->DIER |= (TIM_DIER_CC1IE << channel);
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/* calculate time till timeout */
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value = (value - dev(tim)->CNT) & timer_config[tim].max;
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if (value > timeout) {
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/* time till timeout is larger than requested --> timer already expired
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* ==> let's make sure we have an IRQ pending :) */
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dev(tim)->EGR |= (TIM_EGR_CC1G << channel);
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}
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irq_restore(irqstate);
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return 0;
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}
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#ifdef MODULE_PERIPH_TIMER_PERIODIC
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int timer_set_periodic(tim_t tim, int channel, unsigned int value, uint8_t flags)
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{
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if (channel >= (int)TIMER_CHANNEL_NUMOF) {
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return -1;
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}
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unsigned irqstate = irq_disable();
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clear_oneshot(tim, channel);
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if (flags & TIM_FLAG_SET_STOPPED) {
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timer_stop(tim);
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}
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if (flags & TIM_FLAG_RESET_ON_SET) {
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/* setting COUNT gives us an interrupt on all channels */
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dev(tim)->CNT = 0;
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/* wait for the interrupt & clear it */
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while(dev(tim)->SR == 0) {}
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dev(tim)->SR = 0;
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}
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TIM_CHAN(tim, channel) = value;
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/* clear spurious IRQs */
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dev(tim)->SR &= ~(TIM_SR_CC1IF << channel);
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/* enable IRQ */
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dev(tim)->DIER |= (TIM_DIER_CC1IE << channel);
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if (flags & TIM_FLAG_RESET_ON_MATCH) {
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dev(tim)->ARR = value;
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}
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irq_restore(irqstate);
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return 0;
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}
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#endif /* MODULE_PERIPH_TIMER_PERIODIC */
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int timer_clear(tim_t tim, int channel)
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{
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if (channel >= (int)TIMER_CHANNEL_NUMOF) {
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return -1;
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}
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unsigned irqstate = irq_disable();
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dev(tim)->DIER &= ~(TIM_DIER_CC1IE << channel);
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irq_restore(irqstate);
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#ifdef MODULE_PERIPH_TIMER_PERIODIC
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if (dev(tim)->ARR == TIM_CHAN(tim, channel)) {
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dev(tim)->ARR = timer_config[tim].max;
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}
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#endif
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return 0;
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}
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unsigned int timer_read(tim_t tim)
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{
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return (unsigned int)dev(tim)->CNT;
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}
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void timer_start(tim_t tim)
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{
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unsigned irqstate = irq_disable();
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dev(tim)->CR1 |= TIM_CR1_CEN;
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irq_restore(irqstate);
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}
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void timer_stop(tim_t tim)
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{
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unsigned irqstate = irq_disable();
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dev(tim)->CR1 &= ~(TIM_CR1_CEN);
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irq_restore(irqstate);
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}
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static inline void irq_handler(tim_t tim)
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{
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uint32_t top = dev(tim)->ARR;
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uint32_t status = dev(tim)->SR & dev(tim)->DIER;
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dev(tim)->SR = 0;
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for (unsigned int i = 0; status; i++) {
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uint32_t msk = TIM_SR_CC1IF << i;
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/* check if interrupt flag is set */
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if ((status & msk) == 0) {
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continue;
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}
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status &= ~msk;
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/* interrupt flag gets set for all channels > ARR */
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if (TIM_CHAN(tim, i) > top) {
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continue;
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}
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/* disable Interrupt */
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if (is_oneshot(tim, i)) {
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dev(tim)->DIER &= ~msk;
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}
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isr_ctx[tim].cb(isr_ctx[tim].arg, i);
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}
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cortexm_isr_end();
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}
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#ifdef TIMER_0_ISR
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void TIMER_0_ISR(void)
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{
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irq_handler(0);
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}
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#endif
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#ifdef TIMER_1_ISR
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void TIMER_1_ISR(void)
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{
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irq_handler(1);
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}
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#endif
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#ifdef TIMER_2_ISR
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void TIMER_2_ISR(void)
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{
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irq_handler(2);
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}
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#endif
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#ifdef TIMER_3_ISR
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void TIMER_3_ISR(void)
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{
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irq_handler(3);
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}
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#endif
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#ifdef TIMER_4_ISR
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void TIMER_4_ISR(void)
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{
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irq_handler(4);
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}
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#endif
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