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https://github.com/RIOT-OS/RIOT.git
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120 lines
3.8 KiB
C
120 lines
3.8 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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* Copyright (C) 2014 PHYTEC Messtechnik GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @defgroup cpu_kw2x KW2xD SiP
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* @ingroup cpu
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* @brief CPU specific implementations for the Freescale KW2xD SiP.
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* The SiP incorporates a low power 2.4 GHz transceiver and a
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* Kinetis Cortex-M4 MCU.
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* @{
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*
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* @file
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* @brief Implementation specific CPU configuration options
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*
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* @author Hauke Petersen <hauke.peterse@fu-berlin.de>
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* @author Johann Fischer <j.fischer@phytec.de>
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*/
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#ifndef CPU_CONF_H
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#define CPU_CONF_H
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#include "cpu_conf_common.h"
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#ifdef CPU_MODEL_KW21D256
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#include "MKW22D5.h"
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#elif CPU_MODEL_KW21D512
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#include "MKW22D5.h"
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#elif CPU_MODEL_KW22D512
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#include "MKW22D5.h"
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#else
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#error "undefined CPU_MODEL"
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#endif
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @brief ARM Cortex-M specific CPU configuration
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* @{
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*/
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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#define CPU_IRQ_NUMOF (65U)
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#define CPU_FLASH_BASE (0x00000000)
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/** @} */
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/**
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* @name GPIO pin mux function numbers
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*/
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/** @{ */
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#define PIN_MUX_FUNCTION_ANALOG 0
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#define PIN_MUX_FUNCTION_GPIO 1
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/** @} */
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/**
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* @name GPIO interrupt flank settings
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*/
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/** @{ */
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#define PIN_INTERRUPT_RISING 0b1001
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#define PIN_INTERRUPT_FALLING 0b1010
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#define PIN_INTERRUPT_EDGE 0b1011
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/** @} */
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/** @name PORT module clock gates */
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/** @{ */
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#define PORTA_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT))
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#define PORTB_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT))
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#define PORTC_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT))
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#define PORTD_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT))
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#define PORTE_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT))
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/** @} */
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/**
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* @brief MCU specific Low Power Timer settings.
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*/
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#define LPTIMER_CLKSRC LPTIMER_CLKSRC_LPO
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#define LPTIMER_DEV (LPTMR0) /**< LPTIMER hardware module */
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#define LPTIMER_CLKEN() (SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK) /**< Enable LPTMR0 clock gate */
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#define LPTIMER_CLKDIS() (SIM->SCGC5 &= ~SIM_SCGC5_PTMR_MASK) /**< Disable LPTMR0 clock gate */
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#define LPTIMER_CNR_NEEDS_LATCHING 1 /**< LPTMR.CNR register do not need latching */
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/**
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* @name KW2XD SiP internal interconnects between MCU and Modem.
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*
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* @{
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*/
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#define KW2XDRF_PORT_DEV PORTB /**< MCU Port connected to Modem*/
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#define KW2XDRF_PORT PORT_B /**< MCU Port connected to Modem*/
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#define KW2XDRF_GPIO GPIOB /**< GPIO Device connected to Modem */
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#define KW2XDRF_PORT_IRQn PORTB_IRQn
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/** Clock Enable for PORTB*/
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#define KW2XDRF_PORT_CLKEN() (PORTB_CLOCK_GATE = 1)
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#define KW2XDRF_PIN_AF 2 /**< Pin Muxing Parameter for GPIO Device*/
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#define KW2XDRF_PCS0_PIN 10 /**< SPI Slave Select Pin */
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#define KW2XDRF_SCK_PIN 11 /**< SPI Clock Output Pin */
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#define KW2XDRF_SOUT_PIN 16 /**< SPI Master Data Output Pin */
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#define KW2XDRF_SIN_PIN 17 /**< SPI Master Data Input Pin */
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#define KW2XDRF_RST_PIN 19 /**< Reset pin */
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#define KW2XDRF_IRQ_PIN 3 /**< Modem's IRQ Output (activ low) */
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#define KW2XDRF_CLK_CTRL_PORT PORT_C /**< CLK_OUT control pin port */
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#define KW2XDRF_CLK_CTRL_PORT_DEV PORTC /**< CLK_OUT control pin PORT device */
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#define KW2XDRF_CLK_CTRL_GPIO GPIOC /**< CLK_OUT control pin GPIO device */
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#define KW2XDRF_CLK_CTRL_CLKEN() (PORTC_CLOCK_GATE = 1)
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#define KW2XDRF_CLK_CTRL_PIN 0 /**< CLK_OUT control pin */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPU_CONF_H */
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/** @} */
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