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45 lines
858 B
C
45 lines
858 B
C
/*
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* Copyright (C) 2019 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Common configuration for STM32 RTT
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef CFG_RTT_DEFAULT_H
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#define CFG_RTT_DEFAULT_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name RTT configuration
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*
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* On the STM32Lx platforms, we always utilize the LPTIM1.
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* @{
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*/
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#define RTT_NUMOF (1)
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#define RTT_FREQUENCY (1024U) /* 32768 / 2^n */
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#define RTT_MAX_VALUE (0x0000ffff) /* 16-bit timer */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CFG_RTT_DEFAULT_H */
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/** @} */
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