mirror of
https://github.com/RIOT-OS/RIOT.git
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193 lines
5.8 KiB
C
193 lines
5.8 KiB
C
/*
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* Copyright (C) 2017 Mesotic SAS
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup drivers_adxl345
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* @{
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*
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* @file
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* @brief Register and bit definitions for the ADXL345
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*
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* @author Dylan Laduranty <dylan.laduranty@mesotic.com>
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*/
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#ifndef ADXL345_REGS_H
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#define ADXL345_REGS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Register addresses
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* @{
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*/
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#define ADXL345_CHIP_ID_REG (0x00) /**< Device ID */
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#define ADXL345_THRESH_TAP (0x1D) /**< Tap threshold */
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#define ADXL345_OFFSET_X (0x1E) /**< X-axis offset */
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#define ADXL345_OFFSET_Y (0x1F) /**< Y-axis offset */
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#define ADXL345_OFFSET_Z (0x20) /**< Z-axis offset */
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#define ADXL345_TAP_DUR (0x21) /**< Tap duration */
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#define ADXL345_TAP_LAT (0x22) /**< Tap latency */
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#define ADXL345_TAP_WIN (0x23) /**< Tap window */
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#define ADXL345_THRESH_ACT (0x24) /**< Activity threshold */
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#define ADXL345_THRESH_INACT (0x25) /**< Inactivity threshold */
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#define ADXL345_TIME_INACT (0x26) /**< Inactivity time */
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#define ADXL345_ACT_INACT_CTL (0x27) /**< Axis enable control for activity and inactivity detection */
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#define ADXL345_THRESH_FF (0x28) /**< Free-fall threshold */
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#define ADXL345_TIME_FF (0x29) /**< Free-fall time */
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#define ADXL345_TAP_AXES (0x2A) /**< Axis control for single tap/double tap */
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#define ADXL345_ACT_TAP_STATUS (0x2B) /**< Source of single tap/double tap */
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#define ADXL345_BW_RATE (0x2C) /**< Data rate and power mode control */
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#define ADXL345_POWER_CTL (0x2D) /**< Power-saving features control */
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#define ADXL345_INT_ENABLE (0x2E) /**< Interrupt enable control */
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#define ADXL345_INT_MAP (0x2F) /**< Interrupt mapping control */
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#define ADXL345_INT_SOURCE (0x30) /**< Source of interrupts */
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#define ADXL345_DATA_FORMAT (0x31) /**< Data format control */
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#define ADXL345_DATA_X0 (0x32) /**< X-Axis Data 0 */
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#define ADXL345_DATA_X1 (0x33) /**< X-Axis Data 1 */
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#define ADXL345_DATA_Y0 (0x34) /**< Y-Axis Data 0 */
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#define ADXL345_DATA_Y1 (0x35) /**< Y-Axis Data 1 */
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#define ADXL345_DATA_Z0 (0x36) /**< Z-Axis Data 0 */
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#define ADXL345_DATA_Z1 (0x37) /**< Z-Axis Data 1 */
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#define ADXL345_FIFO_CTL (0x38) /**< FIFO control */
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#define ADXL345_FIFO_STATUS (0x39) /**< FIFO status */
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/** @} */
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/**
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* @name Device ID for ADXL345
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* @{
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*/
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#define ADXL345_CHIP_ID (0xE5)
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/** @} */
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/**
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* @name Resolution masks for output data
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* @{
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*/
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#define ADXL345_RES_10_BITS (0x03FF)
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#define ADXL345_RES_11_BITS (0x07FF)
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#define ADXL345_RES_12_BITS (0x0FFF)
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#define ADXL345_RES_13_BITS (0x1FFF)
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/** @} */
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/**
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* @name bits definitions for ACT_INACT_CTL register
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* @{
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*/
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#define ADXL345_INACT_Z_ENABLE (1 << 0)
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#define ADXL345_INACT_Y_ENABLE (1 << 1)
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#define ADXL345_INACT_X_ENABLE (1 << 2)
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#define ADXL345_INACT_ACDC (1 << 3)
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#define ADXL345_ACT_Z_ENABLE (1 << 4)
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#define ADXL345_ACT_Y_ENABLE (1 << 5)
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#define ADXL345_ACT_X_ENABLE (1 << 6)
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#define ADXL345_ACT_ACDC (1 << 7)
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/** @} */
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/**
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* @name bits definitions for TAP_AXES register
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* @{
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*/
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#define ADXL345_TAP_Z_ENABLE (1 << 0)
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#define ADXL345_TAP_Y_ENABLE (1 << 1)
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#define ADXL345_TAP_X_ENABLE (1 << 2)
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#define ADXL345_SUPPRESS (1 << 3)
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#define ADXL345_TAP_ALL_ENABLE (ADXL345_TAP_Z_ENABLE | \
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ADXL345_TAP_Y_ENABLE | \
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ADXL345_TAP_X_ENABLE)
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/** @} */
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/**
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* @name bits definitions for ACT_TAP_STATUS register
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* @{
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*/
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#define ADXL345_TAP_Z_SRC (1 << 0)
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#define ADXL345_TAP_Y_SRC (1 << 1)
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#define ADXL345_TAP_X_SRC (1 << 2)
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#define ADXL345_ASLEEP (1 << 3)
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#define ADXL345_ACT_Z_SRC (1 << 4)
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#define ADXL345_ACT_Y_SRC (1 << 5)
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#define ADXL345_ACT_X_SRC (1 << 6)
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/** @} */
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/**
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* @name bits definitions for BW_RATE register
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* @{
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*/
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#define ADXL345_RATE_MASK (0x0F)
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#define ADXL345_LOWPOWER (1 << 4)
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/** @} */
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/**
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* @name bits definitions for PWR_CTL register
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* @{
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*/
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#define ADXL345_WAKEUP_8HZ (0x00)
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#define ADXL345_WAKEUP_4HZ (0x01)
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#define ADXL345_WAKEUP_2HZ (0x02)
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#define ADXL345_WAKEUP_1HZ (0x03)
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#define ADXL345_SLEEP_BIT (1 << 2)
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#define ADXL345_MEASURE_BIT (1 << 3)
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#define ADXL345_AUTOSLEEP_BIT (1 << 4)
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#define ADXL345_LINK_BIT (1 << 5)
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/** @} */
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/**
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* @name interrupts pins definitions for INT_ENABLE, INT_MAP and INT_SOURCE
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* registers
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* @{
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*/
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#define ADXL345_OVERRUN (1 << 0)
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#define ADXL345_WATERMARK (1 << 1)
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#define ADXL345_FREEFALL (1 << 2)
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#define ADXL345_INACTIVITY (1 << 3)
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#define ADXL345_ACTIVITY (1 << 4)
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#define ADXL345_DOUBLE_TAP (1 << 5)
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#define ADXL345_SINGLE_TAP (1 << 6)
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#define ADXL345_DATA_READY (1 << 7)
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/** @} */
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/**
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* @name bits definitions for DATA_FORMAT register
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* @{
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*/
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#define ADXL345_RANGE_MASK (0x03)
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#define ADXL345_JUSTIFY (1 << 2)
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#define ADXL345_FULL_RES (1 << 3)
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#define ADXL345_INT_INVERT (1 << 5)
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#define ADXL345_SPI_BIT (1 << 6)
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#define ADXL345_SELF_TEST (1 << 7)
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/** @} */
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/**
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* @name bits definitions for FIFO_CTL register
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* @{
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*/
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#define ADXL345_SAMPLES_MASK (0x0F)
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#define ADXL345_FIFO_TRIGGER_POS (4)
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#define ADXL345_FIFO_TRIGGER (1 << ADXL345_FIFO_TRIGGER_POS)
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#define ADXL345_FIFO_MODE_POS (6)
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#define ADXL345_FIFO_MODE_MASK (0xC0)
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/** @} */
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/**
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* @name bits definitions for FIFO_STATUS register
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* @{
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*/
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#define ADXL345_FIFO_ENTRIES_MASK (0x3F)
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#define ADXL345_FIFO_TRIG (1 << 7)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ADXL345_REGS_H */
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/** @} */
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