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7d1d5e77d8
New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
32 lines
821 B
C
32 lines
821 B
C
// See LICENSE for license details.
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#ifndef _SIFIVE_UART_H
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#define _SIFIVE_UART_H
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/* Register offsets */
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#define UART_REG_TXFIFO 0x00
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#define UART_REG_RXFIFO 0x04
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#define UART_REG_TXCTRL 0x08
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#define UART_REG_RXCTRL 0x0c
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#define UART_REG_IE 0x10
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#define UART_REG_IP 0x14
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#define UART_REG_DIV 0x18
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/* TXFIFO register */
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#define UART_TXFIFO_FULL (1 << 31)
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#define UART_RXFIFO_EMPTY (1 << 31)
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/* TXCTRL register */
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#define UART_TXEN 0x1
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#define UART_TXWM(x) (((x) & 0xffff) << 16)
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/* RXCTRL register */
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#define UART_RXEN 0x1
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#define UART_RXWM(x) (((x) & 0xffff) << 16)
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/* IP register */
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#define UART_IP_TXWM 0x1
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#define UART_IP_RXWM 0x2
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#endif /* _SIFIVE_UART_H */
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