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165 lines
3.9 KiB
C
165 lines
3.9 KiB
C
/*
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* Copyright (C) 2021 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief STM32WL CPU specific definitions for internal peripheral handling
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*
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* @author Akshai M <akshai.m@fu-berlin.de>
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*
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*/
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#ifndef PERIPH_WL_PERIPH_CPU_H
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#define PERIPH_WL_PERIPH_CPU_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef DOXYGEN
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/**
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* @brief ADC voltage regulator start-up time [us]
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*/
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#define ADC_T_ADCVREG_STUP_US (20)
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/**
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* @brief Available number of ADC devices
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*/
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#define ADC_DEVS (1U)
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/**
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* @brief Override ADC resolution values
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* @{
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*/
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#define HAVE_ADC_RES_T
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typedef enum {
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ADC_RES_6BIT = (ADC_CFGR1_RES), /**< ADC resolution: 6 bit */
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ADC_RES_8BIT = (ADC_CFGR1_RES_1), /**< ADC resolution: 8 bit */
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ADC_RES_10BIT = (ADC_CFGR1_RES_0), /**< ADC resolution: 10 bit */
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ADC_RES_12BIT = (0x0), /**< ADC resolution: 12 bit */
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ADC_RES_14BIT = (0x1), /**< not applicable */
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ADC_RES_16BIT = (0x2) /**< not applicable */
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} adc_res_t;
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/** @} */
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/**
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* @brief Starting address of the ROM bootloader
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* see application note AN2606 ( Table 143 : System memory)
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*/
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#define STM32_BOOTLOADER_ADDR (0x1FFF0000)
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/**
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* @name Constants for internal VBAT ADC line
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* @{
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*/
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#define VBAT_ADC_RES ADC_RES_12BIT
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#define VBAT_ADC_MAX 4095
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @defgroup cpu_stm32_wl_debug STM32WL hardware debugging
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* @ingroup cpu_stm32
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* @{
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*/
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/**
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* @defgroup cpu_stm32_wl_debug_subghz_spi STM32WL Sub-GHz SPI debug pins
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* @ingroup cpu_stm32_wl_debug
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* @{
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*/
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#define CPU_STM32WL_SUBGHZSPI_DEBUG_MOSIOUT GPIO_PIN(PORT_A, 7)
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#define CPU_STM32WL_SUBGHZSPI_DEBUG_MOSIOUT_AF GPIO_AF13
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#define CPU_STM32WL_SUBGHZSPI_DEBUG_MISOOUT GPIO_PIN(PORT_A, 6)
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#define CPU_STM32WL_SUBGHZSPI_DEBUG_MISOOUT_AF GPIO_AF13
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#define CPU_STM32WL_SUBGHZSPI_DEBUG_SCKOUT GPIO_PIN(PORT_A, 5)
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#define CPU_STM32WL_SUBGHZSPI_DEBUG_SCKOUT_AF GPIO_AF13
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#define CPU_STM32WL_SUBGHZSPI_DEBUG_NSSOUT GPIO_PIN(PORT_A, 4)
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#define CPU_STM32WL_SUBGHZSPI_DEBUG_NSSOUT_AF GPIO_AF13
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/** @} */
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/** @} */
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/**
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* @defgroup cpu_stm32_wl_debug_subghz_radio STM32WL Sub-GHz Radio debug pins
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* @ingroup cpu_stm32_wl_debug
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* @{
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*/
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/*!
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* RF BUSY debug pin definition
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*/
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#define CPU_STM32WL_SUBGHZ_RF_BUSY GPIO_PIN(PORT_A, 12)
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/*!
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* RF BUSY debug pin alternate function
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*/
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#define CPU_STM32WL_SUBGHZ_RF_BUSY_AF GPIO_AF6
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/*!
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* RF NRESET debug pin definition
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*/
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#define CPU_STM32WL_SUBGHZ_DEBUG_RF_NRESET GPIO_PIN(PORT_A, 11)
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/*!
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* RF NRESET debug pin alternate function
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*/
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#define CPU_STM32WL_SUBGHZ_DEBUG_RF_NRESET_AF GPIO_AF13
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/*!
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* RF SMPSRDY debug pin definition
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*/
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#define CPU_STM32WL_SUBGHZ_DEBUG_RF_SMPSRDY GPIO_PIN(PORT_B, 2)
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/*!
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* RF SMPSRDY debug pin alternate function
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*/
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#define CPU_STM32WL_SUBGHZ_DEBUG_RF_SMPSRDY_AF GPIO_AF13
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/*!
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* RF LDORDY debug pin definition
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*/
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#define CPU_STM32WL_SUBGHZ_DEBUG_RF_LDORDY GPIO_PIN(PORT_B, 4)
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/*!
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* RF LDORDY debug pin alternate function
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*/
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#define CPU_STM32WL_SUBGHZ_DEBUG_RF_LDORDY_AF GPIO_AF13
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/*!
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* RF HSE32RDY debug pin definition
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*/
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#define CPU_STM32WL_SUBGHZ_DEBUG_RF_HSE32RDY GPIO_PIN(PORT_A, 10)
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/*!
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* RF HSE32RDY debug pin alternate function
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*/
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#define CPU_STM32WL_SUBGHZ_DEBUG_RF_HSE32RDY_AF GPIO_AF13
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/** @} */
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/**
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* @defgroup cpu_stm32_wl_config STM32WL compile time configuration
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* @ingroup cpu_stm32_wl_debug
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* @ingroup config_cpu
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* @{
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*/
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/**
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* @brief Set this to 1 to enable hardware debugging.
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*/
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#ifdef DOXYGEN
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#define CONFIG_STM32_WLX5XX_SUBGHZ_DEBUG
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#endif
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_WL_PERIPH_CPU_H */
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/** @} */
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