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a2e1b92e1d
For RISC-V and Cortex-M-not-3, triples are known and have worked in some configuration, but do not work at the moment and stay disabled until the reference platforms (native, M3) have been established well.
62 lines
2.3 KiB
Makefile
62 lines
2.3 KiB
Makefile
# Target architecture for the build.
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# The correct triple for 32 bit embedded RISC-V targets is "riscv32-none-elf".
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# However, is unknown is used as sys (in place of none), it will also fall back
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# to none. Finally, if the GCC RISC-V cross compiler is compiled with full
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# multilib support, it can create both 32 bit and 64 bit binaries. Often this is
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# indicated with "riscv" being used instead of "riscv32/riscv64", but e.g.
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# Ubuntu uses "riscv64-unknown-elf" despite being able to produce both 32 and
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# 64 bit binaries. We'll test all possible combinations from the most correct
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# triple to the least correct triple all that might be able to produce our
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# binaries. Finally, "riscv-none-embed" is also tested for compatibility with
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# an previously popular legacy toolchain.
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# For a CI transition period, it is tested first.
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_TRIPLES_TO_TEST := \
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riscv-none-embed \
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riscv32-none-elf \
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riscv-none-elf \
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riscv32-unknown-elf \
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riscv-unknown-elf \
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riscv64-none-elf \
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riscv64-unknown-elf
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TARGET_ARCH_RISCV ?= \
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$(strip \
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$(subst -gcc,,\
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$(notdir \
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$(word 1,\
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$(foreach triple,$(_TRIPLES_TO_TEST),$(shell which $(triple)-gcc 2> /dev/null))))))
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TARGET_ARCH ?= $(TARGET_ARCH_RISCV)
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# define build specific options
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CFLAGS_CPU = -march=rv32imac -mabi=ilp32
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ifeq ($(TOOLCHAIN),llvm)
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# Always use riscv32-none-elf as target triple for clang, as some
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# autodetected gcc target triples are incompatible with clang
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TARGET_ARCH_LLVM := riscv32-none-elf
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else
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CFLAGS_CPU += -mcmodel=medlow -msmall-data-limit=8
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ifneq (,$(shell $(TARGET_ARCH)-gcc --help=target | grep '\-malign-data='))
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CFLAGS_CPU += -malign-data=natural
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endif
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endif
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CFLAGS_LINK = -ffunction-sections -fdata-sections
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CFLAGS_DBG ?= -g3
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CFLAGS_OPT ?= -Os
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LINKFLAGS += -L$(RIOTCPU)/$(CPU)/ldscripts -L$(RIOTCPU)/riscv_common/ldscripts
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LINKER_SCRIPT ?= $(CPU_MODEL).ld
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LINKFLAGS += -T$(LINKER_SCRIPT)
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CFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) $(CFLAGS_OPT) $(CFLAGS_LINK)
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ASFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG)
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# export linker flags
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LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_LINK) $(CFLAGS_DBG) $(CFLAGS_OPT) -nostartfiles -Wl,--gc-sections -static -lgcc
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# Platform triple as used by Rust
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RUST_TARGET = riscv32imac-unknown-none-elf
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# Workaround for https://github.com/rust-lang/rust-bindgen/issues/1555
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CARGO_EXTRACFLAGS += --target=riscv32
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