mirror of
https://github.com/RIOT-OS/RIOT.git
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287 lines
8.4 KiB
C
287 lines
8.4 KiB
C
/*
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* Copyright (C) 2017 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_frdm-k22f
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* @{
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*
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* @file
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* @name Peripheral MCU configuration for the FRDM-K22F
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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static const clock_config_t clock_config = {
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/*
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* This configuration results in the system running from the FLL output with
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* the following clock frequencies:
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* Core: 60 MHz
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* Bus: 30 MHz
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* Flex: 20 MHz
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* Flash: 20 MHz
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*/
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.clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |
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SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(2),
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.default_mode = KINETIS_MCG_MODE_FEE,
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/* The crystal connected to OSC0 is 8 MHz */
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.erc_range = KINETIS_MCG_ERC_RANGE_HIGH,
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.fcrdiv = 0, /* Fast IRC divide by 1 => 4 MHz */
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.oscsel = 0, /* Use OSC0 for external clock */
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.clc = 0, /* External load caps on the FRDM-K22F board */
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.fll_frdiv = 0b011, /* Divide by 256 */
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.fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
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.fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1920, /* FLL freq = 60 MHz */
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.pll_prdiv = 0b00011, /* Divide by 4 */
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.pll_vdiv = 0b00110, /* Multiply by 30 => PLL freq = 60 MHz */
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.enable_oscillator = true,
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.select_fast_irc = true,
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.enable_mcgirclk = false,
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};
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#define CLOCK_CORECLOCK (60000000ul)
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#define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 2)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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#define PIT_NUMOF (2U)
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#define PIT_CONFIG { \
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{ \
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.prescaler_ch = 0, \
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.count_ch = 1, \
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}, \
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{ \
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.prescaler_ch = 2, \
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.count_ch = 3, \
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}, \
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}
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#define LPTMR_NUMOF (1U)
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#define LPTMR_CONFIG { \
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{ \
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.dev = LPTMR0, \
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.irqn = LPTMR0_IRQn, \
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} \
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}
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#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
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#define PIT_BASECLOCK (CLOCK_BUSCLOCK)
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#define PIT_ISR_0 isr_pit1
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#define PIT_ISR_1 isr_pit3
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#define LPTMR_ISR_0 isr_lptmr0
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = UART1,
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.freq = CLOCK_CORECLOCK,
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.pin_rx = GPIO_PIN(PORT_E, 1),
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.pin_tx = GPIO_PIN(PORT_E, 0),
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.pcr_rx = PORT_PCR_MUX(3),
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.pcr_tx = PORT_PCR_MUX(3),
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.irqn = UART1_RX_TX_IRQn,
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.scgc_addr = &SIM->SCGC4,
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.scgc_bit = SIM_SCGC4_UART1_SHIFT,
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.mode = UART_MODE_8N1,
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.type = KINETIS_UART,
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},
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};
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#define UART_0_ISR (isr_uart1_rx_tx)
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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static const adc_conf_t adc_config[] = {
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/* dev, pin, channel */
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{ .dev = ADC0, .pin = GPIO_UNDEF , .chan = 0 }, /* ADC0_DP0 */
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{ .dev = ADC0, .pin = GPIO_UNDEF , .chan = 19 }, /* ADC0_DM0 */
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{ .dev = ADC1, .pin = GPIO_UNDEF , .chan = 0 }, /* ADC1_DP0 */
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{ .dev = ADC1, .pin = GPIO_UNDEF , .chan = 19 }, /* ADC1_DM0 */
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{ .dev = ADC0, .pin = GPIO_PIN(PORT_B, 0), .chan = 8 }, /* PTB0 (Arduino A0) */
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{ .dev = ADC0, .pin = GPIO_PIN(PORT_B, 1), .chan = 9 }, /* PTB1 (Arduino A1) */
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{ .dev = ADC0, .pin = GPIO_PIN(PORT_C, 1), .chan = 15 }, /* PTC1 (Arduino A2) */
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{ .dev = ADC0, .pin = GPIO_PIN(PORT_C, 2), .chan = 4 }, /* PTC2 (Arduino A3) */
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};
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#define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.ftm = FTM0,
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.chan = {
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{ .pin = GPIO_PIN(PORT_A, 1), .af = 3, .ftm_chan = 6 },
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{ .pin = GPIO_PIN(PORT_A, 2), .af = 3, .ftm_chan = 7 },
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{ .pin = GPIO_PIN(PORT_D, 5), .af = 4, .ftm_chan = 5 },
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},
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.chan_numof = 3,
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.ftm_num = 0
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}
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};
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#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
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/** @} */
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/**
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* @name SPI configuration
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*
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* Clock configuration values based on the configured 48Mhz module clock.
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*
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* Auto-generated by:
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* cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
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*
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* @{
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*/
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static const uint32_t spi_clk_config[] = {
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(
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SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93750Hz */
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SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
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SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
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SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
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),
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(
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SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 375000Hz */
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SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
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SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
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SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
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),
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(
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SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 1000000Hz */
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SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
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SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
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SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
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),
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(
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SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4800000Hz */
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SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
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SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
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SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
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),
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(
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SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 8000000Hz */
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SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
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SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
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SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
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)
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI0,
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.pin_miso = GPIO_PIN(PORT_D, 3),
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.pin_mosi = GPIO_PIN(PORT_D, 2),
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.pin_clk = GPIO_PIN(PORT_D, 1),
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.pin_cs = {
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GPIO_PIN(PORT_C, 4),
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GPIO_PIN(PORT_D, 4),
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GPIO_UNDEF,
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GPIO_UNDEF,
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GPIO_UNDEF
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},
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.pcr = GPIO_AF_2,
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.simmask = SIM_SCGC6_SPI0_MASK
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}
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};
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#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_NUMOF (1U)
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#define I2C_0_EN 1
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/* Low (10 kHz): MUL = 2, SCL divider = 1536, total: 3072 */
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#define KINETIS_I2C_F_ICR_LOW (0x36)
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#define KINETIS_I2C_F_MULT_LOW (1)
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/* Normal (100 kHz): MUL = 2, SCL divider = 160, total: 320 */
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#define KINETIS_I2C_F_ICR_NORMAL (0x1D)
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#define KINETIS_I2C_F_MULT_NORMAL (1)
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/* Fast (400 kHz): MUL = 1, SCL divider = 80, total: 80 */
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#define KINETIS_I2C_F_ICR_FAST (0x14)
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#define KINETIS_I2C_F_MULT_FAST (0)
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/* Fast plus (1000 kHz): MUL = 1, SCL divider = 30, total: 30 */
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#define KINETIS_I2C_F_ICR_FAST_PLUS (0x05)
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#define KINETIS_I2C_F_MULT_FAST_PLUS (0)
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/* I2C 0 device configuration */
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#define I2C_0_DEV I2C0
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#define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C0_MASK))
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#define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C0_MASK))
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#define I2C_0_IRQ I2C0_IRQn
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#define I2C_0_IRQ_HANDLER isr_i2c0
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/* I2C 0 pin configuration */
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#define I2C_0_PORT PORTB
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#define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK))
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#define I2C_0_PIN_AF 2
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#define I2C_0_SDA_PIN 3
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#define I2C_0_SCL_PIN 2
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#define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
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/** @} */
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/**
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* @name RTT and RTC configuration
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* @{
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*/
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#define RTT_NUMOF (1U)
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#define RTC_NUMOF (1U)
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#define RTT_DEV RTC
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#define RTT_IRQ RTC_IRQn
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#define RTT_IRQ_PRIO 10
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#define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
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#define RTT_ISR isr_rtc
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#define RTT_FREQUENCY (1)
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#define RTT_MAX_VALUE (0xffffffff)
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/** @} */
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/**
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* @name Random Number Generator configuration
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* @{
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*/
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#define KINETIS_RNGA RNG
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#define HWRNG_CLKEN() (SIM->SCGC6 |= (1 << 9))
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#define HWRNG_CLKDIS() (SIM->SCGC6 &= ~(1 << 9))
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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