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a2e1b92e1d
For RISC-V and Cortex-M-not-3, triples are known and have worked in some configuration, but do not work at the moment and stay disabled until the reference platforms (native, M3) have been established well.
48 lines
1.1 KiB
Plaintext
48 lines
1.1 KiB
Plaintext
# Copyright (c) 2020 Inria
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#
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# This file is subject to the terms and conditions of the GNU Lesser
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# General Public License v2.1. See the file LICENSE in the top level
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# directory for more details.
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config CPU_ARCH_RISCV
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bool
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select HAS_ARCH_RISCV
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select HAS_CPP
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select HAS_LIBSTDCPP
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select HAS_NEWLIB
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select HAS_PERIPH_CORETIMER
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select HAS_PICOLIBC if '$(RIOT_CI_BUILD)' != '1'
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#select HAS_RUST_TARGET
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select HAS_SSP
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select MODULE_MALLOC_THREAD_SAFE if TEST_KCONFIG
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imply MODULE_NEWLIB_NANO
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config CPU_CORE_RV32IMAC
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bool
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select CPU_ARCH_RISCV
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select HAS_ARCH_32BIT
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## Definition of specific features
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config HAS_ARCH_RISCV
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bool
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help
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Indicates that the current CPU has a RISC-V.
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config CPU_ARCH
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default "rv32" if CPU_CORE_RV32IMAC
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config MODULE_RISCV_COMMON
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bool
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default y
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depends on TEST_KCONFIG && CPU_ARCH_RISCV
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select MODULE_MALLOC_THREAD_SAFE
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help
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Common code for RISC-V architecture.
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rsource "periph/Kconfig"
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choice LIBC_IMPLEMENTATION
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default MODULE_NEWLIB
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endchoice
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