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116 lines
3.2 KiB
C
116 lines
3.2 KiB
C
/*
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* Copyright (C) 2015-2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief STM32F1 CPU specific definitions for internal peripheral handling
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef PERIPH_F1_PERIPH_CPU_H
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#define PERIPH_F1_PERIPH_CPU_H
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#include "cpu_conf.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef DOXYGEN
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/**
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* @brief Starting address of the ROM bootloader
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* see application note AN2606
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*/
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#if defined(CPU_LINE_STM32F103xB) || defined(CPU_LINE_STM32F103xE)
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#define STM32_BOOTLOADER_ADDR (0x1FFFF000)
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#endif
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/**
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* @brief Readout Protection (RDP) option bytes
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*/
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#define STM32_OPTION_BYTES ((uint32_t*) 0x1FFFF800)
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#define GET_RDP(x) (x & 0xFF)
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#endif /* ndef DOXYGEN */
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/**
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* @name Real time counter configuration
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* @{
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*/
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#define RTT_IRQ_PRIO 1
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#define RTT_DEV RTC
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#define RTT_IRQ RTC_IRQn
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#define RTT_ISR isr_rtc
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#define RTT_MAX_VALUE (0xffffffff)
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#define RTT_CLOCK_FREQUENCY (32768U) /* in Hz */
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#define RTT_MIN_FREQUENCY (1U) /* in Hz */
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/* RTC frequency of 32kHz is not recommended, see RM0008 Rev 20, p490 */
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#define RTT_MAX_FREQUENCY (RTT_CLOCK_FREQUENCY / 2) /* in Hz */
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/** @} */
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/**
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* @brief Available number of ADC devices
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*/
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#define ADC_DEVS (2U)
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/**
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* @name GPIO Definitions Missing in Vendor Files
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* @{
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*/
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/**
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* @brief Possible values of the MODE0 field in the GPIO CRL register
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*
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* The MODE1 to MODE7 fields have the same values. Don't forget to shift the
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* constants to the field position for MODE1 to MODE7 by 4 times n bits, where
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* n is the pin number.
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*
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* In addition the MODE8 to MODE15 fields in the CRH register have the same
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* layout and semantics as the MODE0 to MODE 7 fields in the CRL register.
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*/
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enum {
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GPIO_CRL_MODE0_INPUT = (0x0 << GPIO_CRL_MODE0_Pos),
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GPIO_CRL_MODE0_OUTPUT_10MHZ = (0x1 << GPIO_CRL_MODE0_Pos),
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GPIO_CRL_MODE0_OUTPUT_2MHZ = (0x2 << GPIO_CRL_MODE0_Pos),
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GPIO_CRL_MODE0_OUTPUT_50MHZ = (0x3 << GPIO_CRL_MODE0_Pos),
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};
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/**
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* @brief Possible values of the CNF0 field in the GPIO CRL register
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*
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* The CNF1 to CNF7 fields have the same values. Don't forget to shift the
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* constants to the field position for CNF1 to CNF7 by 4 times n bits, where
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* n is the pin number.
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*
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* In addition the CNF8 to CNF15 fields in the CRH register have the same
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* layout and semantics as the CNF0 to CNF 7 fields in the CRL register.
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*/
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enum {
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GPIO_CRL_CNF0_INPUT_ANALOG = (0x0 << GPIO_CRL_CNF0_Pos),
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GPIO_CRL_CNF0_INPUT_FLOATING = (0x1 << GPIO_CRL_CNF0_Pos),
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GPIO_CRL_CNF0_INPUT_PULL = (0x2 << GPIO_CRL_CNF0_Pos),
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GPIO_CRL_CNF0_OUTPUT_PUSH_PULL = (0x0 << GPIO_CRL_CNF0_Pos),
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GPIO_CRL_CNF0_OUTPUT_OPEN_DRAIN = (0x1 << GPIO_CRL_CNF0_Pos),
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GPIO_CRL_CNF0_AF_PUSH_PULL = (0x2 << GPIO_CRL_CNF0_Pos),
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GPIO_CRL_CNF0_AF_OPEN_DRAIN = (0x3 << GPIO_CRL_CNF0_Pos),
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};
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_F1_PERIPH_CPU_H */
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/** @} */
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