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https://github.com/RIOT-OS/RIOT.git
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283 lines
6.4 KiB
C
283 lines
6.4 KiB
C
/*
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* Copyright (C) 2014 Loci Controls Inc.
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* 2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc2538
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* @ingroup drivers_periph_gpio
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* @{
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*
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* @file
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* @brief Low-level GPIO driver implementation
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*
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* @author Ian Martin <ian@locicontrols.com>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Sebastian Meiling <s@mlng.net>
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* @}
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*/
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#include <stdint.h>
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#include "cpu.h"
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#include "periph/gpio.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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#define MODE_NOTSUP (0xff)
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#ifdef MODULE_PERIPH_GPIO_IRQ
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static gpio_isr_ctx_t isr_ctx[4][8];
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#endif /* MODULE_PERIPH_GPIO_IRQ */
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/**
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* @brief Access GPIO low-level device
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*
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* @param[in] pin gpio pin
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*
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* @return pointer to gpio low level device address
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*/
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static inline cc2538_gpio_t *gpio(gpio_t pin)
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{
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return (cc2538_gpio_t *)(pin & GPIO_PORT_MASK);
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}
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/**
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* @brief Helper function to get port number for gpio pin
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*
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* @param[in] pin gpio pin
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*
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* @return port number of gpio pin, [0=A - 3=D]
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*/
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static inline uint8_t _port_num(gpio_t pin)
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{
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return (uint8_t)((pin & GPIO_PORTNUM_MASK) >> GPIO_PORTNUM_SHIFT) - 1;
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}
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/**
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* @brief Helper function to get pin number for gpio pin
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*
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* @param[in] pin gpio pin
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*
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* @return pin number of gpio pin, [0 - 7]
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*/
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static inline uint8_t _pin_num(gpio_t pin)
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{
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return (uint8_t)(pin & GPIO_PIN_MASK);
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}
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/**
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* @brief Helper function to get bit mask for gpio pin number
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*
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* @param[in] pin gpio pin
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*
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* @return bit mask for gpio pin number, 2^[0 - 7]
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*/
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static inline uint32_t _pin_mask(gpio_t pin)
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{
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return (1 << (pin & GPIO_PIN_MASK));
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}
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/**
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* @brief Helper function to get CC2538 gpio number from port and pin
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*
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* @param[in] pin gpio pin
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*
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* @return number of gpio pin, [0 - 31]
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*/
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static inline uint8_t _pp_num(gpio_t pin)
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{
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return (uint8_t)((_port_num(pin) * GPIO_BITS_PER_PORT) + _pin_num(pin));
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}
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int gpio_init(gpio_t pin, gpio_mode_t mode)
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{
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/* check if mode is valid */
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if (mode == MODE_NOTSUP) {
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return -1;
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}
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DEBUG("GPIO %"PRIu32", PORT: %u, PIN: %u\n", (uint32_t)pin, _port_num(pin), _pin_num(pin));
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/* disable any alternate function and any eventual interrupts */
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gpio(pin)->IE &= ~_pin_mask(pin);
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gpio(pin)->AFSEL &= ~_pin_mask(pin);
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/* configure pull configuration */
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IOC->OVER[_pp_num(pin)] = mode;
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/* set pin direction */
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if (mode == GPIO_OUT) {
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gpio(pin)->DIR |= _pin_mask(pin);
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}
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else {
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gpio(pin)->DIR &= ~_pin_mask(pin);
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}
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return 0;
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}
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int gpio_read(gpio_t pin)
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{
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return (int)(gpio(pin)->DATA & _pin_mask(pin));
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}
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void gpio_set(gpio_t pin)
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{
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gpio(pin)->DATA |= _pin_mask(pin);
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}
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void gpio_clear(gpio_t pin)
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{
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gpio(pin)->DATA &= ~_pin_mask(pin);
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}
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void gpio_toggle(gpio_t pin)
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{
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gpio(pin)->DATA ^= _pin_mask(pin);
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}
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void gpio_write(gpio_t pin, int value)
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{
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if (value) {
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gpio(pin)->DATA |= _pin_mask(pin);
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}
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else {
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gpio(pin)->DATA &= ~_pin_mask(pin);
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}
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}
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#ifdef MODULE_PERIPH_GPIO_IRQ
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int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
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gpio_cb_t cb, void *arg)
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{
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if (gpio_init(pin, mode) != 0) {
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return -1;
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}
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/* store the callback information for later: */
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isr_ctx[_port_num(pin)][_pin_num(pin)].cb = cb;
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isr_ctx[_port_num(pin)][_pin_num(pin)].arg = arg;
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/* enable power-up interrupts for this GPIO port: */
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SYS_CTRL->IWE |= (1 << _port_num(pin));
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/* configure the active flank(s) */
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gpio(pin)->IS &= ~_pin_mask(pin);
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switch(flank) {
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case GPIO_FALLING:
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gpio(pin)->IBE &= ~_pin_mask(pin);
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gpio(pin)->IEV &= ~_pin_mask(pin);
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gpio(pin)->P_EDGE_CTRL |= (1 << _pp_num(pin));
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break;
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case GPIO_RISING:
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gpio(pin)->IBE &= ~_pin_mask(pin);
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gpio(pin)->IEV |= _pin_mask(pin);
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gpio(pin)->P_EDGE_CTRL &= ~(1 << _pp_num(pin));
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break;
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case GPIO_BOTH:
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gpio(pin)->IBE |= _pin_mask(pin);
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break;
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default:
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return -1;
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}
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/* reset interrupt status */
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gpio(pin)->IC = _pin_mask(pin);
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gpio(pin)->PI_IEN |= (1 << _pp_num(pin));
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/* enable global interrupt for the selected GPIO port */
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NVIC_EnableIRQ(GPIO_PORT_A_IRQn + _port_num(pin));
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/* unmask pin interrupt */
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gpio(pin)->IE |= _pin_mask(pin);
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return 0;
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}
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void gpio_irq_enable(gpio_t pin)
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{
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gpio(pin)->IE |= _pin_mask(pin);
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}
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void gpio_irq_disable(gpio_t pin)
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{
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gpio(pin)->IE &= ~_pin_mask(pin);
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}
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static inline void handle_isr(uint8_t port_num)
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{
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cc2538_gpio_t *port = ((cc2538_gpio_t *)GPIO_BASE) + port_num;
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uint32_t state = port->MIS;
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port->IC = 0x000000ff;
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port->IRQ_DETECT_ACK = (0xff << (port_num * GPIO_BITS_PER_PORT));
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for (int i = 0; i < GPIO_BITS_PER_PORT; i++) {
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if (state & (1 << i)) {
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isr_ctx[port_num][i].cb(isr_ctx[port_num][i].arg);
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}
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}
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cortexm_isr_end();
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}
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/** @brief Interrupt service routine for Port A */
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void isr_gpioa(void)
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{
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handle_isr(0);
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}
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/** @brief Interrupt service routine for Port B */
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void isr_gpiob(void)
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{
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handle_isr(1);
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}
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/** @brief Interrupt service routine for Port C */
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void isr_gpioc(void)
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{
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handle_isr(2);
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}
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/** @brief Interrupt service routine for Port D */
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void isr_gpiod(void)
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{
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handle_isr(3);
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}
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#endif /* MODULE_PERIPH_GPIO_IRQ */
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/* CC2538 specific add-on GPIO functions */
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void gpio_init_af(gpio_t pin, uint8_t sel, uint8_t over)
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{
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assert(pin != GPIO_UNDEF);
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IOC->OVER[_pp_num(pin)] = over;
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if (over != GPIO_OUT) {
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IOC->PINS[sel] = _pp_num(pin);
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}
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else {
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IOC->SEL[_pp_num(pin)] = sel;
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}
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/* enable alternative function mode */
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gpio(pin)->AFSEL |= _pin_mask(pin);
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}
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void gpio_init_mux(gpio_t pin, uint8_t over, uint8_t sel, uint8_t func)
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{
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assert(pin != GPIO_UNDEF);
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/* configure pin function and multiplexing */
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if (over != GPIO_MUX_NONE) {
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IOC->OVER[_pp_num(pin)] = over;
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}
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if (sel != GPIO_MUX_NONE) {
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IOC->SEL[_pp_num(pin)] = sel;
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}
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if (func != GPIO_MUX_NONE) {
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IOC->PINS[func] = _pp_num(pin);
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}
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/* enable alternative function mode */
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gpio(pin)->AFSEL |= _pin_mask(pin);
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}
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