mirror of
https://github.com/RIOT-OS/RIOT.git
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286 lines
10 KiB
C
286 lines
10 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup board_iot-lab_M3
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* @{
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*
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* @file periph_conf.h
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* @brief Peripheral MCU configuration for the iot-lab_M3 board
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*
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef __PERIPH_CONF_H
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#define __PERIPH_CONF_H
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/**
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* @name Clock system configuration
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* @{
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**/
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#define CLOCK_HSE (16000000U) /* frequency of external oscillator */
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#define CLOCK_CORECLOCK (72000000U) /* targeted core clock frequency */
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/* configuration of PLL prescaler and multiply values */
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/* CORECLOCK := HSE / PLL_HSE_DIV * PLL_HSE_MUL */
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#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLXTPRE_HSE_Div2
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#define CLOCK_PLL_HSE_MUL RCC_CFGR_PLLMULL9
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/* configuration of peripheral bus clock prescalers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 72MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 72MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* APB1 clock -> 36MHz */
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/* configuration of flash access cycles */
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2
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/** @} */
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/**
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* @brief Timer configuration
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* @{
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*/
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#define TIMER_NUMOF (2U)
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#define TIMER_0_EN 1
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#define TIMER_1_EN 1
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/* Timer 0 configuration */
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#define TIMER_0_DEV_0 TIM2
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#define TIMER_0_DEV_1 TIM3
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#define TIMER_0_CHANNELS 4
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#define TIMER_0_PRESCALER (72U)
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#define TIMER_0_MAX_VALUE (0xffff)
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#define TIMER_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN))
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#define TIMER_0_ISR_0 isr_tim2
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#define TIMER_0_ISR_1 isr_tim3
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#define TIMER_0_IRQ_CHAN_0 TIM2_IRQn
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#define TIMER_0_IRQ_CHAN_1 TIM3_IRQn
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#define TIMER_0_IRQ_PRIO 1
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#define TIMER_0_TRIG_SEL TIM_SMCR_TS_0
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/* Timer 1 configuration */
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#define TIMER_1_DEV_0 TIM4
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#define TIMER_1_DEV_1 TIM5
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#define TIMER_1_CHANNELS 4
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#define TIMER_1_PRESCALER (36000U)
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#define TIMER_1_MAX_VALUE (0xffff)
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#define TIMER_1_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN | RCC_APB1ENR_TIM5EN))
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#define TIMER_1_ISR_0 isr_tim4
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#define TIMER_1_ISR_1 isr_tim5
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#define TIMER_1_IRQ_CHAN_0 TIM4_IRQn
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#define TIMER_1_IRQ_CHAN_1 TIM5_IRQn
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#define TIMER_1_IRQ_PRIO 1
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#define TIMER_1_TRIG_SEL TIM_SMCR_TS_1
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/** @} */
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/**
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* @brief UART configuration
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*/
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#define UART_NUMOF (1U)
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#define UART_0_EN 1
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#define UART_1_EN 0
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#define UART_IRQ_PRIO 1
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/* UART 0 device configuration */
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#define UART_0_DEV USART1
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#define UART_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_USART1EN)
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#define UART_0_IRQ USART1_IRQn
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#define UART_0_ISR isr_usart1
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#define UART_0_BUS_FREQ 72000000
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/* UART 0 pin configuration */
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#define UART_0_PORT GPIOA
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#define UART_0_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
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#define UART_0_RX_PIN 10
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#define UART_0_TX_PIN 9
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#define UART_0_AF 0
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/* UART 1 device configuration */
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#define UART_1_DEV USART2
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#define UART_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
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#define UART_1_IRQ USART2_IRQn
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#define UART_1_ISR isr_usart2
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#define UART_1_BUS_FREQ 36000000
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/* UART 1 pin configuration */
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#define UART_1_PORT GPIOA
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#define UART_1_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
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#define UART_1_RX_PIN 3
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#define UART_1_TX_PIN 2
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#define UART_1_AF 1
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/**
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* @brief GPIO configuration
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*/
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#define GPIO_NUMOF 15
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#define GPIO_0_EN 1
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#define GPIO_1_EN 1
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#define GPIO_2_EN 1
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#define GPIO_3_EN 1
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#define GPIO_4_EN 1
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#define GPIO_5_EN 1
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#define GPIO_6_EN 1
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#define GPIO_7_EN 1
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#define GPIO_8_EN 1
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#define GPIO_9_EN 1
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#define GPIO_10_EN 1
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#define GPIO_11_EN 1
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#define GPIO_12_EN 1
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#define GPIO_13_EN 1
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#define GPIO_14_EN 1
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#define GPIO_IRQ_PRIO 1
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/**
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* @brief IRQ config
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*
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* These defines are used for the backmapping in the matching interrupt
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* service routines to call the correct callbacks.
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* GPIO_IRQ_x where x matches the value defined by GPIO_y_PIN
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*/
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#define GPIO_IRQ_1 GPIO_13
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#define GPIO_IRQ_2 GPIO_14
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#define GPIO_IRQ_3 GPIO_0
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#define GPIO_IRQ_4 GPIO_12
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#define GPIO_IRQ_5 GPIO_8
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#define GPIO_IRQ_6 GPIO_9
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#define GPIO_IRQ_7 GPIO_5
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#define GPIO_IRQ_8 GPIO_1
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#define GPIO_IRQ_9 GPIO_4
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#define GPIO_IRQ_11 GPIO_7
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#define GPIO_IRQ_12 GPIO_2
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#define GPIO_IRQ_13 GPIO_9
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#define GPIO_IRQ_14 GPIO_10
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/* GPIO channel 0 config */
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#define GPIO_0_PORT GPIOA /* Used for user button 1 */
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#define GPIO_0_PIN 3
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#define GPIO_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
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#define GPIO_0_EXTI_CFG() (AFIO->EXTICR[0] |= AFIO_EXTICR1_EXTI3_PA)
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#define GPIO_0_IRQ EXTI3_IRQn
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/* GPIO channel 1 config */
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#define GPIO_1_PORT GPIOA
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#define GPIO_1_PIN 8
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#define GPIO_1_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
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#define GPIO_1_EXTI_CFG() (AFIO->EXTICR[2] |= AFIO_EXTICR3_EXTI8_PA)
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#define GPIO_1_IRQ EXTI9_5_IRQn
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/* GPIO channel 2 config */
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#define GPIO_2_PORT GPIOA
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#define GPIO_2_PIN 12
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#define GPIO_2_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
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#define GPIO_2_EXTI_CFG() (AFIO->EXTICR[3] |= AFIO_EXTICR4_EXTI12_PA)
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#define GPIO_2_IRQ EXTI15_10_IRQn
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/* GPIO channel 3 config */
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#define GPIO_3_PORT GPIOB
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#define GPIO_3_PIN 8
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#define GPIO_3_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
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#define GPIO_3_EXTI_CFG() (AFIO->EXTICR[2] |= AFIO_EXTICR3_EXTI8_PB)
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#define GPIO_3_IRQ EXTI9_5_IRQn
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/* GPIO channel 4 config */
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#define GPIO_4_PORT GPIOB
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#define GPIO_4_PIN 9
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#define GPIO_4_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
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#define GPIO_4_EXTI_CFG() (AFIO->EXTICR[2] |= AFIO_EXTICR3_EXTI9_PB)
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#define GPIO_4_IRQ EXTI9_5_IRQn
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/* GPIO channel 5 config */
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#define GPIO_5_PORT GPIOC
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#define GPIO_5_PIN 7
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#define GPIO_5_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPCEN)
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#define GPIO_5_EXTI_CFG() (AFIO->EXTICR[1] |= AFIO_EXTICR2_EXTI7_PC)
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#define GPIO_5_IRQ EXTI9_5_IRQn
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/* GPIO channel 6 config */
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#define GPIO_6_PORT GPIOC
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#define GPIO_6_PIN 8
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#define GPIO_6_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPCEN)
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#define GPIO_6_EXTI_CFG() (AFIO->EXTICR[2] |= AFIO_EXTICR3_EXTI8_PC)
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#define GPIO_6_IRQ EXTI9_5_IRQn
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/* GPIO channel 7 config */
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#define GPIO_7_PORT GPIOC
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#define GPIO_7_PIN 11
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#define GPIO_7_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPCEN)
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#define GPIO_7_EXTI_CFG() (AFIO->EXTICR[2] |= AFIO_EXTICR3_EXTI11_PC)
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#define GPIO_7_IRQ EXTI15_10_IRQn
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/* GPIO channel 8 config */
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#define GPIO_8_PORT GPIOA
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#define GPIO_8_PIN 5
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#define GPIO_8_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
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#define GPIO_8_EXTI_CFG() (AFIO->EXTICR[1] |= AFIO_EXTICR2_EXTI5_PA)
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#define GPIO_8_IRQ EXTI9_5_IRQn
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/* GPIO channel 9 config */
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#define GPIO_9_PORT GPIOA
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#define GPIO_9_PIN 6
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#define GPIO_9_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
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#define GPIO_9_EXTI_CFG() (AFIO->EXTICR[1] |= AFIO_EXTICR2_EXTI6_PA)
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#define GPIO_9_IRQ EXTI9_5_IRQn
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/* GPIO channel 10 config */
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#define GPIO_10_PORT GPIOA
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#define GPIO_10_PIN 7
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#define GPIO_10_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
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#define GPIO_10_EXTI_CFG() (AFIO->EXTICR[1] |= AFIO_EXTICR2_EXTI7_PA)
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#define GPIO_10_IRQ EXTI9_5_IRQn
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/* GPIO channel 11 config */
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#define GPIO_11_PORT GPIOA
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#define GPIO_11_PIN 4
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#define GPIO_11_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
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#define GPIO_11_EXTI_CFG() (AFIO->EXTICR[1] |= AFIO_EXTICR2_EXTI4_PA)
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#define GPIO_11_IRQ EXTI4_IRQn
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/* GPIO channel 12 config */
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#define GPIO_12_PORT GPIOC
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#define GPIO_12_PIN 4
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#define GPIO_12_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPCEN)
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#define GPIO_12_EXTI_CFG() (AFIO->EXTICR[1] |= AFIO_EXTICR2_EXTI4_PC)
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#define GPIO_12_IRQ EXTI4_IRQn
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/* GPIO channel 13 config */
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#define GPIO_13_PORT GPIOC
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#define GPIO_13_PIN 1
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#define GPIO_13_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPCEN)
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#define GPIO_13_EXTI_CFG() (AFIO->EXTICR[0] |= AFIO_EXTICR1_EXTI1_PC)
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#define GPIO_13_IRQ EXTI1_IRQn
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/* GPIO channel 14 config */
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#define GPIO_14_PORT GPIOA
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#define GPIO_14_PIN 2
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#define GPIO_14_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
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#define GPIO_14_EXTI_CFG() (AFIO->EXTICR[0] |= AFIO_EXTICR1_EXTI2_PA)
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#define GPIO_14_IRQ EXTI2_IRQn
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/**
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* @brief SPI configuration
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* @{
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*/
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#define SPI_NUMOF (1U)
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#define SPI_0_EN 1
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/* SPI 0 device configuration */
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#define SPI_0_DEV SPI1
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#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
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#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
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#define SPI_0_BUS_DIV 1 /* 1 -> SPI runs with full CPU clock, 0 -> half CPU clock */
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/* SPI 0 pin configuration */
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#define SPI_0_CLK_PORT GPIOA
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#define SPI_0_CLK_PIN 5
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#define SPI_0_CLK_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
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#define SPI_0_MOSI_PORT GPIOA
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#define SPI_0_MOSI_PIN 7
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#define SPI_0_MOSI_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
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#define SPI_0_MISO_PORT GPIOA
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#define SPI_0_MISO_PIN 6
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#define SPI_0_MISO_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
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/** @} */
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/**
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* @name Real time counter configuration
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* @{
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*/
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#define RTT_NUMOF (1U)
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#define RTT_IRQ_PRIO 1
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#define RTT_DEV RTC
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#define RTT_IRQ RTC_IRQn
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#define RTT_ISR isr_rtc
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#define RTT_MAX_VALUE (0xffffffff)
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#define RTT_FREQUENCY (1) /* in Hz */
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#define RTT_PRESCALER (0x7fff) /* run with 1 Hz */
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/** @} */
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#endif /* __PERIPH_CONF_H */
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/** @} */
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