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306 lines
14 KiB
C
306 lines
14 KiB
C
/******************************************************************************
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* Filename: hw_aux_anaif_h
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* Revised: 2017-05-30 11:42:02 +0200 (Tue, 30 May 2017)
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* Revision: 49074
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_AUX_ANAIF_H__
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#define __HW_AUX_ANAIF_H__
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//*****************************************************************************
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//
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// This section defines the register offsets of
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// AUX_ANAIF component
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//
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//*****************************************************************************
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// ADC Control
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#define AUX_ANAIF_O_ADCCTL 0x00000010
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// ADC FIFO Status
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#define AUX_ANAIF_O_ADCFIFOSTAT 0x00000014
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// ADC FIFO
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#define AUX_ANAIF_O_ADCFIFO 0x00000018
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// ADC Trigger
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#define AUX_ANAIF_O_ADCTRIG 0x0000001C
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// Current Source Control
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#define AUX_ANAIF_O_ISRCCTL 0x00000020
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//*****************************************************************************
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//
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// Register: AUX_ANAIF_O_ADCCTL
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//
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//*****************************************************************************
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// Field: [13] START_POL
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//
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// Select active polarity for START_SRC event.
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// ENUMs:
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// FALL Set ADC trigger on falling edge of event source.
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// RISE Set ADC trigger on rising edge of event source.
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#define AUX_ANAIF_ADCCTL_START_POL 0x00002000
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#define AUX_ANAIF_ADCCTL_START_POL_BITN 13
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#define AUX_ANAIF_ADCCTL_START_POL_M 0x00002000
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#define AUX_ANAIF_ADCCTL_START_POL_S 13
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#define AUX_ANAIF_ADCCTL_START_POL_FALL 0x00002000
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#define AUX_ANAIF_ADCCTL_START_POL_RISE 0x00000000
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// Field: [12:8] START_SRC
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//
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// Select ADC trigger event source from the asynchronous AUX event bus.
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//
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// Set START_SRC to NO_EVENT<n> if you want to trigger the ADC manually through
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// ADCTRIG.START.
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// ENUMs:
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// ADC_IRQ AUX_EVCTL:EVSTAT1.ADC_IRQ
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// MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV
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// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF
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// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15
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// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14
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// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13
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// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12
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// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11
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// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10
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// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9
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// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8
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// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7
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// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6
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// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5
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// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4
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// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3
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// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
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// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
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// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
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// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU
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// AON_SW AUX_EVCTL:EVSTAT0.AON_SW
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// NO_EVENT1 No event.
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// NO_EVENT0 No event.
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// RESERVED1 Reserved - Do not use.
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// RESERVED0 Reserved - Do not use.
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// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE
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// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV
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// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV
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// TDC_DONE AUX_EVCTL:EVSTAT0.TDC_DONE
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// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB
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// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA
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// RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2
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#define AUX_ANAIF_ADCCTL_START_SRC_W 5
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#define AUX_ANAIF_ADCCTL_START_SRC_M 0x00001F00
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#define AUX_ANAIF_ADCCTL_START_SRC_S 8
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#define AUX_ANAIF_ADCCTL_START_SRC_ADC_IRQ 0x00001F00
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#define AUX_ANAIF_ADCCTL_START_SRC_MCU_EV 0x00001E00
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#define AUX_ANAIF_ADCCTL_START_SRC_ACLK_REF 0x00001D00
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#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO15 0x00001C00
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#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO14 0x00001B00
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#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO13 0x00001A00
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#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO12 0x00001900
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#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO11 0x00001800
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#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO10 0x00001700
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#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO9 0x00001600
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#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO8 0x00001500
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#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO7 0x00001400
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#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO6 0x00001300
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#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO5 0x00001200
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#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO4 0x00001100
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#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO3 0x00001000
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#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO2 0x00000F00
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#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO1 0x00000E00
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#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO0 0x00000D00
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#define AUX_ANAIF_ADCCTL_START_SRC_AON_PROG_WU 0x00000C00
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#define AUX_ANAIF_ADCCTL_START_SRC_AON_SW 0x00000B00
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#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT1 0x00000A00
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#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT0 0x00000900
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#define AUX_ANAIF_ADCCTL_START_SRC_RESERVED1 0x00000800
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#define AUX_ANAIF_ADCCTL_START_SRC_RESERVED0 0x00000700
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#define AUX_ANAIF_ADCCTL_START_SRC_SMPH_AUTOTAKE_DONE 0x00000600
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#define AUX_ANAIF_ADCCTL_START_SRC_TIMER1_EV 0x00000500
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#define AUX_ANAIF_ADCCTL_START_SRC_TIMER0_EV 0x00000400
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#define AUX_ANAIF_ADCCTL_START_SRC_TDC_DONE 0x00000300
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#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPB 0x00000200
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#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPA 0x00000100
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#define AUX_ANAIF_ADCCTL_START_SRC_RTC_CH2_EV 0x00000000
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// Field: [1:0] CMD
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//
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// ADC interface command.
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//
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// Non-enumerated values are not supported. The written value is returned when
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// read.
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// ENUMs:
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// FLUSH Flush ADC FIFO.
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//
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// You must set CMD to EN or
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// DIS after flush.
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//
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// System CPU must wait two
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// clock cycles before it sets CMD to EN or DIS.
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// EN Enable ADC interface.
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// DIS Disable ADC interface.
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#define AUX_ANAIF_ADCCTL_CMD_W 2
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#define AUX_ANAIF_ADCCTL_CMD_M 0x00000003
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#define AUX_ANAIF_ADCCTL_CMD_S 0
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#define AUX_ANAIF_ADCCTL_CMD_FLUSH 0x00000003
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#define AUX_ANAIF_ADCCTL_CMD_EN 0x00000001
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#define AUX_ANAIF_ADCCTL_CMD_DIS 0x00000000
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//*****************************************************************************
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//
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// Register: AUX_ANAIF_O_ADCFIFOSTAT
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//
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//*****************************************************************************
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// Field: [4] OVERFLOW
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//
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// FIFO overflow flag.
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//
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// 0: FIFO has not overflowed.
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// 1: FIFO has overflowed, this flag is sticky until you flush the FIFO.
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//
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// When the flag is set, the ADC FIFO write pointer is static. It is not
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// possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag.
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#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW 0x00000010
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#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_BITN 4
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#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M 0x00000010
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#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_S 4
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// Field: [3] UNDERFLOW
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//
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// FIFO underflow flag.
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//
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// 0: FIFO has not underflowed.
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// 1: FIFO has underflowed, this flag is sticky until you flush the FIFO.
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//
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// When the flag is set, the ADC FIFO read pointer is static. Read returns the
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// previous sample that was read. Flush FIFO to clear the flag.
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#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW 0x00000008
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#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_BITN 3
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#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M 0x00000008
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#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_S 3
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// Field: [2] FULL
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//
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// FIFO full flag.
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//
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// 0: FIFO is not full, there is less than 4 samples in the FIFO.
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// 1: FIFO is full, there are 4 samples in the FIFO.
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//
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// When the flag is set, it is not possible to add more samples to the ADC
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// FIFO. An attempt to add samples sets the OVERFLOW flag.
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#define AUX_ANAIF_ADCFIFOSTAT_FULL 0x00000004
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#define AUX_ANAIF_ADCFIFOSTAT_FULL_BITN 2
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#define AUX_ANAIF_ADCFIFOSTAT_FULL_M 0x00000004
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#define AUX_ANAIF_ADCFIFOSTAT_FULL_S 2
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// Field: [1] ALMOST_FULL
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//
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// FIFO almost full flag.
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//
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// 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL
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// flag is also asserted in the latter case.
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// 1: There are 3 samples in the FIFO, there is room for one more sample.
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#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL 0x00000002
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#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_BITN 1
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#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M 0x00000002
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#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_S 1
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// Field: [0] EMPTY
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//
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// FIFO empty flag.
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//
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// 0: FIFO contains one or more samples.
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// 1: FIFO is empty.
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//
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// When the flag is set, read returns the previous sample that was read and
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// sets the UNDERFLOW flag.
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#define AUX_ANAIF_ADCFIFOSTAT_EMPTY 0x00000001
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#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_BITN 0
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#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_M 0x00000001
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#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_S 0
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//*****************************************************************************
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//
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// Register: AUX_ANAIF_O_ADCFIFO
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//
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//*****************************************************************************
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// Field: [11:0] DATA
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//
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// FIFO data.
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//
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// Read:
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// Get oldest ADC sample from FIFO.
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//
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// Write:
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// Write dummy sample to FIFO. This is useful for code development when you do
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// not have real ADC samples.
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#define AUX_ANAIF_ADCFIFO_DATA_W 12
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#define AUX_ANAIF_ADCFIFO_DATA_M 0x00000FFF
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#define AUX_ANAIF_ADCFIFO_DATA_S 0
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//*****************************************************************************
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//
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// Register: AUX_ANAIF_O_ADCTRIG
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//
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//*****************************************************************************
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// Field: [0] START
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//
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// Manual ADC trigger.
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//
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// 0: No effect.
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// 1: Single ADC trigger.
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//
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// To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT<n> to
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// avoid conflict with event-driven ADC trigger.
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#define AUX_ANAIF_ADCTRIG_START 0x00000001
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#define AUX_ANAIF_ADCTRIG_START_BITN 0
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#define AUX_ANAIF_ADCTRIG_START_M 0x00000001
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#define AUX_ANAIF_ADCTRIG_START_S 0
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//*****************************************************************************
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//
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// Register: AUX_ANAIF_O_ISRCCTL
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//
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//*****************************************************************************
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// Field: [0] RESET_N
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//
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// ISRC reset control.
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//
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// 0: ISRC drives 0 uA.
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// 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN.
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#define AUX_ANAIF_ISRCCTL_RESET_N 0x00000001
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#define AUX_ANAIF_ISRCCTL_RESET_N_BITN 0
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#define AUX_ANAIF_ISRCCTL_RESET_N_M 0x00000001
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#define AUX_ANAIF_ISRCCTL_RESET_N_S 0
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#endif // __AUX_ANAIF__
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