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https://github.com/RIOT-OS/RIOT.git
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107 lines
3.8 KiB
C
107 lines
3.8 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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* Copyright (C) 2013 INRIA
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup drivers_cc110x
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* @{
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*
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* @file cc110x-config.h
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* @brief Configuration parameters for the cc110x radio chip
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*
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* @author Oliver Hahm <oliver.hahm@inria.fr>
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* @author Fabian Nack <nack@inf.fu-berlin.de>
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*/
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#ifndef CC110X_CONFIG_H
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#define CC110X_CONFIG_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief CC110x register configuration
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*/
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typedef struct {
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uint8_t _IOCFG2; /**< GDO2 output pin configuration */
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uint8_t _IOCFG1; /**< GDO1 output pin configuration */
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uint8_t _IOCFG0; /**< GDO0 output pin configuration */
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uint8_t _FIFOTHR; /**< RX FIFO and TX FIFO thresholds */
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uint8_t _SYNC1; /**< Sync word, high byte */
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uint8_t _SYNC0; /**< Sync word, low byte */
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uint8_t _PKTLEN; /**< Packet length */
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uint8_t _PKTCTRL1; /**< Packet automation control */
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uint8_t _PKTCTRL0; /**< Packet automation control */
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uint8_t _ADDR; /**< Device address */
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uint8_t _CHANNR; /**< Channel number */
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uint8_t _FSCTRL1; /**< Frequency synthesizer control */
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uint8_t _FSCTRL0; /**< Frequency synthesizer control */
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uint8_t _FREQ2; /**< Frequency control word, high byte */
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uint8_t _FREQ1; /**< Frequency control word, middle byte */
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uint8_t _FREQ0; /**< Frequency control word, low byte */
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uint8_t _MDMCFG4; /**< Modem configuration */
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uint8_t _MDMCFG3; /**< Modem configuration */
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uint8_t _MDMCFG2; /**< Modem configuration */
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uint8_t _MDMCFG1; /**< Modem configuration */
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uint8_t _MDMCFG0; /**< Modem configuration */
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uint8_t _DEVIATN; /**< Modem deviation setting */
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uint8_t _MCSM2; /**< Main Radio Control State Machine configuration */
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uint8_t _MCSM1; /**< Main Radio Control State Machine configuration */
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uint8_t _MCSM0; /**< Main Radio Control State Machine configuration */
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uint8_t _FOCCFG; /**< Frequency Offset Compensation configuration */
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uint8_t _BSCFG; /**< Bit Synchronization configuration */
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uint8_t _AGCCTRL2; /**< AGC control */
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uint8_t _AGCCTRL1; /**< AGC control */
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uint8_t _AGCCTRL0; /**< AGC control */
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uint8_t _WOREVT1; /**< High byte Event 0 timeout */
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uint8_t _WOREVT0; /**< Low byte Event 0 timeout */
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uint8_t _WORCTRL; /**< Wake On Radio control */
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uint8_t _FREND1; /**< Front end RX configuration */
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uint8_t _FREND0; /**< Front end TX configuration */
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uint8_t _FSCAL3; /**< Frequency synthesizer calibration */
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uint8_t _FSCAL2; /**< Frequency synthesizer calibration */
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uint8_t _FSCAL1; /**< Frequency synthesizer calibration */
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uint8_t _FSCAL0; /**< Frequency synthesizer calibration */
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} cc110x_reg_t;
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/**
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* @brief CC110x radio configuration
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*/
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typedef struct {
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cc110x_reg_t reg_cfg; ///< CC1100 register configuration
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uint8_t pa_power; ///< Output power setting
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} cc110x_cfg_t;
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/**
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* @brief Radio Control Flags
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*/
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typedef struct {
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uint8_t _RSSI; ///< The RSSI value of last received packet
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uint8_t _LQI; ///< The LQI value of the last received packet
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} cc110x_flags;
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/**
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* @brief Statistic interface for debugging
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*/
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typedef struct cc110x_statistic {
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uint32_t packets_in;
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uint32_t packets_in_crc_fail;
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uint32_t packets_in_while_tx;
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uint32_t raw_packets_out;
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} cc110x_statistic_t;
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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#endif /* CC110X_CONFIG_H */
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