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https://github.com/RIOT-OS/RIOT.git
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274 lines
6.0 KiB
C
274 lines
6.0 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32f0
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* @{
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*
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* @file
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* @brief Low-level UART driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include "cpu.h"
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#include "board.h"
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#include "sched.h"
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#include "thread.h"
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#include "periph_conf.h"
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#include "periph/uart.h"
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/* guard file in case no UART device was specified */
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#if UART_NUMOF
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/**
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* @brief Each UART device has to store two callbacks.
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*/
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typedef struct {
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uart_rx_cb_t rx_cb;
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uart_tx_cb_t tx_cb;
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void *arg;
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} uart_conf_t;
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/**
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* @brief Unified interrupt handler for all UART devices
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*
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* @param uartnum the number of the UART that triggered the ISR
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* @param uart the UART device that triggered the ISR
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*/
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static inline void irq_handler(uart_t uartnum, USART_TypeDef *uart);
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/**
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* @brief Allocate memory to store the callback functions.
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*/
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static uart_conf_t uart_config[UART_NUMOF];
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static USART_TypeDef *const uart_port[UART_NUMOF] = {
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#if UART_0_EN
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[UART_0] = UART_0_DEV,
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#endif
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#if UART_1_EN
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[UART_1] = UART_1_DEV,
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#endif
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};
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int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, uart_tx_cb_t tx_cb, void *arg)
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{
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int res;
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/* initialize UART in blocking mode first */
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res = uart_init_blocking(uart, baudrate);
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if (res < 0) {
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return res;
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}
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/* enable global interrupt and configure the interrupts priority */
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switch (uart) {
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#if UART_0_EN
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case UART_0:
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NVIC_SetPriority(UART_0_IRQ, UART_IRQ_PRIO);
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NVIC_EnableIRQ(UART_0_IRQ);
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UART_0_DEV->CR1 |= USART_CR1_RXNEIE;
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break;
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#endif
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#if UART_1_EN
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case UART_1:
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NVIC_SetPriority(UART_1_IRQ, UART_IRQ_PRIO);
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NVIC_EnableIRQ(UART_1_IRQ);
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UART_1_DEV->CR1 |= USART_CR1_RXNEIE;
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break;
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#endif
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}
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/* register callbacks */
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uart_config[uart].rx_cb = rx_cb;
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uart_config[uart].tx_cb = tx_cb;
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uart_config[uart].arg = arg;
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return 0;
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}
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int uart_init_blocking(uart_t uart, uint32_t baudrate)
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{
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USART_TypeDef *dev = 0;
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GPIO_TypeDef *port = 0;
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uint32_t rx_pin = 0;
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uint32_t tx_pin = 0;
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uint8_t af = 0;
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uint32_t mid;
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uint16_t mantissa;
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uint8_t fraction;
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/* enable UART and port clocks and select devices */
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switch (uart) {
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#if UART_0_EN
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case UART_0:
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dev = UART_0_DEV;
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port = UART_0_PORT;
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rx_pin = UART_0_RX_PIN;
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tx_pin = UART_0_TX_PIN;
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af = UART_0_AF;
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/* enable clocks */
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UART_0_CLKEN();
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UART_0_PORT_CLKEN();
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break;
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#endif
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#if UART_1_EN
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case UART_1:
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dev = UART_1_DEV;
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port = UART_1_PORT;
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tx_pin = UART_1_TX_PIN;
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rx_pin = UART_1_RX_PIN;
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af = UART_1_AF;
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/* enable clocks */
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UART_1_CLKEN();
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UART_1_PORT_CLKEN();
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break;
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#endif
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}
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/* configure RX and TX pins, set pin to use alternative function mode */
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port->MODER &= ~(3 << (rx_pin * 2) | 3 << (tx_pin * 2));
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port->MODER |= 2 << (rx_pin * 2) | 2 << (tx_pin * 2);
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/* and assign alternative function */
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if (rx_pin < 8) {
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port->AFR[0] &= ~(0xf << (rx_pin * 4));
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port->AFR[0] |= af << (rx_pin * 4);
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}
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else {
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port->AFR[1] &= ~(0xf << ((rx_pin - 16) * 4));
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port->AFR[1] |= af << ((rx_pin - 16) * 4);
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}
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if (tx_pin < 8) {
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port->AFR[0] &= ~(0xf << (tx_pin * 4));
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port->AFR[0] |= af << (tx_pin * 4);
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}
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else {
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port->AFR[1] &= ~(0xf << ((tx_pin - 16) * 4));
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port->AFR[1] |= af << ((tx_pin - 16) * 4);
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}
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/* configure UART to mode 8N1 with given baudrate */
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mid = (CLOCK_CORECLOCK / baudrate);
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mantissa = (uint16_t)(mid / 16);
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fraction = (uint8_t)(mid - (mantissa * 16));
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dev->BRR = ((mantissa & 0x0fff) << 4) | (0x0f & fraction);
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/* enable receive and transmit mode */
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dev->CR1 |= USART_CR1_UE | USART_CR1_TE | USART_CR1_RE;
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return 0;
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}
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void uart_tx_begin(uart_t dev)
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{
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USART_TypeDef *uart = uart_port[dev];
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uart->CR1 |= USART_CR1_TXEIE;
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}
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int uart_write(uart_t dev, char data)
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{
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USART_TypeDef *uart = uart_port[dev];
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if (uart->ISR & USART_ISR_TXE) {
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uart->TDR = (uint8_t)data;
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}
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return 0;
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}
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int uart_read_blocking(uart_t dev, char *data)
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{
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USART_TypeDef *uart = uart_port[dev];
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while (!(uart->ISR & USART_ISR_RXNE));
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*data = (char)uart->RDR;
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return 1;
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}
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int uart_write_blocking(uart_t dev, char data)
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{
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USART_TypeDef *uart = uart_port[dev];
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while (!(uart->ISR & USART_ISR_TXE));
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uart->TDR = (uint8_t)data;
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return 1;
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}
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void uart_poweron(uart_t uart)
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{
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switch (uart) {
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#if UART_0_EN
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case UART_0:
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UART_0_CLKEN();
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break;
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#endif
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#if UART_1_EN
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case UART_1:
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UART_1_CLKEN();
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break;
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#endif
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}
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}
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void uart_poweroff(uart_t uart)
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{
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switch (uart) {
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#if UART_0_EN
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case UART_0:
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UART_0_CLKDIS();
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break;
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#endif
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#if UART_1_EN
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case UART_1:
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UART_1_CLKDIS();
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break;
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#endif
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}
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}
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#if UART_0_EN
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void UART_0_ISR(void)
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{
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irq_handler(UART_0, UART_0_DEV);
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}
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#endif
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#if UART_1_EN
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void UART_1_ISR(void)
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{
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irq_handler(UART_1, UART_1_DEV);
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}
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#endif
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static inline void irq_handler(uint8_t uartnum, USART_TypeDef *dev)
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{
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if (dev->ISR & USART_ISR_RXNE) {
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char data = (char)dev->RDR;
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uart_config[uartnum].rx_cb(uart_config[uartnum].arg, data);
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}
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else if (dev->ISR & USART_ISR_ORE) {
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/* do nothing on overrun */
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dev->ICR |= USART_ICR_ORECF;
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}
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else if (dev->ISR & USART_ISR_TXE) {
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if (uart_config[uartnum].tx_cb(uart_config[uartnum].arg) == 0) {
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dev->CR1 &= ~USART_CR1_TXEIE;
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}
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}
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if (sched_context_switch_request) {
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thread_yield();
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}
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}
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#endif /* UART_NUMOF */
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